2010 CANDE Workshop Program

Sanctuary Beach Resort Hotel, Monterey, California
November 4-6, 2010

Thursday, Nov 4, 6:30 – 9:00 pm: Opening Reception (Cocktails / Open Discussion )
Friday, Nov 5, 7:30 – 8:30 am: Breakfast
Friday, Nov 5, morning:

The Real Deal with 3D : Chaired by Mark Horowitz, Stanford
8:30- 9:15 Dinesh Somaskhar, Intel “Architecture and Design of 3D IC’s”
9:15 – 10:00 Phil Emma, IBM “What Is 3D Really, and What’s It Good For, Really”
10:00 – 10:30 Morning break
10:30 – 11:15 Igor Markov, Michigan “The Road to 3D EDA: Paved with Good Intentions”
11:15 – 11:45 3D Panel and open discussion

Friday, Nov 5, 11:45- 1:45 pm: Lunch
Lunch Keynote: Mark Horowitz, Stanford “Why Design Must Change”
Friday, Nov 5, afternoon:

Looking Beyond EDA: Chaired by William H. Joyner, SRC
1:45 – 2:15 Frank Liu, IBM “Dynamic Simulation of Large Scale River Systems: the Connection between Electrons and Water Molecules”
2:15 – 2:55 Michael Flynn, Stanford / Maxeler “Automating the Acceleration of Very Large Applications”
2:55 – 3:25 Tim Kraska, Berkeley “The Potential of Cloud Computing: Challenges, Opportunities, Impact”
3:25 – 3:55 Afternoon break
3:55 – 4:30 Jason Lohn, CMU “Antenna Design Automation”
4:30 – 5:10 Takahide Inoue, Berkeley / CITRIS “Opinion Space: Looking Beyond EDA/Semiconductor”

Friday, Nov 5, 7:00-9:00 pm: Dinner
Dinner Keynote: Anirudh Devgan, Analog-Mixed Signal: The Next EDA Frontier
Saturday, Nov 6, 7:30-9:00 am: Breakfast
Saturday, Nov 6, morning:

Automatic Security: Chaired by Farinaz Koushanfar
9:00 – 9:40 Miodrag Potkonjak, UCLA “Impossible Problems Caused by Simple Solutions and Simple Solutions for Impossible Problems”
9:40 – 10:20 Robert Lucas, USC Information Sciences Institute, “Imaging Integrated Circuits with 3D X-Ray Microscopy”
10:20 – 10:50 Morning break
10:50 – 11:30 Krishna Samigethay, Boeing, “Cyber-Physical Systems Security”
11:30 – 12:10 Gang Qu, Maryland, “Role of Hardware in Security and a Case Study on PUF”

Saturday, Nov 6, 12:10-1:30: Lunch and CANDE Wrapup

Technical Session Details

The Real Deal with 3D
Dinesh Somaskhar, Intel “Architecture and Design of 3D IC’s”
3D stacking is a key enabler for allowing dissimilar process technologies to be in close physical proximity. It is often viewed as a solution for the problem of high band-width, low latency — high data-rate and high interconnection count — between memory devices and processors. In this space it allows for the most cost-effective solution by leveraging the low cost of a memory process without burdening it with high performance device requirements. While research has often focused on technical challenges of implementing the die stack, namely thermals, die-stackup (memory on top, logic on top) and the technology used for implementing TSVs, less mention is found of the design challenges imposed by perforating a die with TSVs. This talk presents a case study of a stacked 3D chip in 65nm which implements a high bandwidth processor memory stackup. It highlights particular issues and solutions developed with reference to micro-architecture of the overall processor memory hierarchy, power distribution, physical design implications and test. The emphasis of the talk being to highlight the non-trivial design issues imposed by the introduction of TSV perforation on a large logic die.
Dinesh Somasekhar received the B.E. degree in EE from the Maharaja Sayajirao University Baroda in 1989, the M.E degree in from the Indian Institute of Science Bangalore in 1991, and the Ph.D. degree from Purdue in 1995. From 1991 to 1994 he was an I.C. Design Engineer at Texas Instruments, Bangalore, where he designed ASIC compiler memories and interface I.C.s. Since 1999 he has been at the Hillsboro Circuits Research Lab, Intel R&D where he is currently a Senior Staff Research Scientist. He currently works in the area of dense memory technology. He has published 35 papers and holds over 70 patents in the field of VLSI. Dr. Somasekhar served as a mentor at the Semiconductor Research Consortium, and has participated in the Technical Program Committee of ISLPED, DATE, ISQED and GLVLSI.

Phil Emma, IBM “What Is 3D Really, and What’s It Good For, Really”
“3D” is generically used to describe many kinds of structures; some having immediate value in certain markets, but many being of dubiousvalue and/or having real difficulties. We explore this space and make suggestions as to what needs to happen to reap real potential in 3D for high-end markets.
Dr. Philip Emma received his PhD degree in EE from Illinois in 1983, after which he joined IBM Research. He has been a design leader on a number of products, has written numerous technical articles and chapters in several books, and holds well over 100 patents. He now leads the Systems Technology and Microarchitecture group at IBM Watson, which does advanced concept work in architecture and microarchitecture for IBM’s servers, as well as for processors for mobile applications. He is a member of the IBM Academy of Technology, and a Fellow of the IEEE.

Igor Markov, Michigan: “The Road to 3D EDA: Paved with Good Intentions”
As semiconductor scaling laws run into gale force headwinds, 3D die stacking promises to continue increasing silicon integration levels. We will show that most of the academic research in 3D EDA has been misguided, leaving interesting challenges free for the taking.
Bio: Igor L. Markov is an associate professor of Electrical Engineering and Computer Science at the University of Michigan. He is the recipient of an ACM SIGDA Outstanding New Faculty award, an NSF CAREER award, an IBM Partnership Award, a Microsoft A. Richard Newton Breakthrough Research Award, and the inaugural IEEE CEDA Early Career Award. His research focuses on computers that make computers.

Lunch Keynote: Mark Horowitz, Stanford, Why Design Must Change
The slowing performance gains from CMOS scaling and the rising design costs are making it more difficult to continue to deliver value to our customers. To buck this trend, we need to make design much more efficient. In many ways our current situation is reminiscent of the situation in the mid 80′s where chips were custom designed, and only created by chip companies.
Synthesis and placement/routing systems created the ASIC market, and we need a similar scale improvement today. For many reasons I don’t believe that either the current SoC, or high-level language effort will succeed in solving this problem. Instead, we should acknowledge that working out the interactions in a complex design is complex, and will cost a lot of money, even when we do it well. The key is to leverage this work over a broader class of chips. This approach leads to the idea of building chip-generators and not chips. That is instead of building a programmable chip to meet a broad class of application needs, you create a virtual programmable chip, that is MUCH more flexible than any real chip. The application designer (the new chip designer) will then configure this substrate to optimize their application. The generator will take this information and then create the desired chip. While there are many very hard problems that need to be addressed to make this work, but none of them seem insurmountable. In fact I will provide some recent examples from my group which indicate the promise of this approach – including improving the energy efficiency of a H.264 encoder by 200x, and how to validate a chip generator.

Mark Horowitz is the Chair of the Electrical Engineering Department and the Yahoo! Founders Professor at Stanford University, and a founder of Rambus, Inc. He is a fellow of IEEE and ACM and is a member of the National Academy of Engineering and the American Academy of Arts and Science. Dr. Horowitz’s research interests are quite broad and span using EE and CS analysis methods to problems in molecular biology to creating new design methodologies for analog and digital VLSI circuits.

Looking Beyond EDA
Frank Liu, IBM, “Dynamic Simulation of Large Scale River Systems: the Connection between Electrons and Water Molecules”
EDA is about how to make better or cheaper semiconductor chips. However, the techniques can also be applied to other problems which are becoming more important to the society. In this presentation, I will talk about how to use EDA methods to simulate dynamic river systems, which is our closest source of fresh water.
Bio: Frank Liu is a Research Staff Member at IBM Austin Research Lab. He works on various analysis and optimization problems in EDA, as well as variability characterization and computational lithography

Michael Flynn, Stanford / Maxeler, “Automating the acceleration of very large applications”
Very large applications can be accelerated by building customized synchronous data flow machines with FPGAs. We discuss the theory, tools and limitations of this approach as well as some quite promising results.
Michael Flynn has had a long career in computer architecture and design; starting with early IBM mainframes. He was Professor of EE at Stanford for 25 years where he directed the computer architecture and arithmetic group. He is now senior adviser and board chairman at Maxeler Technologies.

Tim Kraska, Berkeley “The Potential of Cloud Computing: Challenges, Opportunities, Impact”
Cloud computing opens up access to large computing resources for medium-sized companies, small startups, and even private persons. As a consequence, cloud computing rapidly changes the IT infrastructure landscape. This talk gives a brief overview of the opportunities and challenges which come with the rise of cloud computing as well as the impact it has on programming models and systems from a user perspective.
Tim Kraska is a PostDoc in the RAD Lab which is part of the Berkeley CS Dept. Currently, his research focuses on data management for cloud-scale analytics, machine learning, and crowd sourcing in the context of the upcoming AMP Lab. Tim received his PhD from ETH Zurich, where he worked on transaction management and stream processing in the cloud at the Systems Group. He also holds a Master of Information Technology from the University of Sydney, Australia, as well as an MSc from the University of Muenster, Germany.

Jason Lohn, CMU “Antenna Design Automation”
Current methods of designing and optimizing antennas by hand are time and labor intensive, limit complexity, and require significant expertise and experience. Stochastic search algorithms can overcome these limitations by automatically searching the design space and finding effective solutions that are closer to limits imposed by physics. For example, our algorithms have discovered antenna designs that have wide impedance bandwidth, are electrically small, highly efficient, and compare well in terms of size, weight, and cost. While optimization modules are commonly available in commercial antenna CAD tools, they are typically simple parametric methods, and no system yet offers an antenna synthesis capability. We discuss the antenna synthesis system we are developing and its use in a variety of applications, focusing on a project that produced antennas that flew in space on NASA’s Space Technology 5 (ST5) mission.
Jason Lohn is an Associate Research Professor at Carnegie Mellon Silicon Valley. Previously he led Evolvable Systems research at NASA Ames Research Center, worked in search quality at Google, was a Visiting Scholar at Stanford, and worked as an engineer at IBM. He received his MS and PhD in EE from Maryland, and his BS in EE from Lehigh. He has over 50 technical publications and his work has been featured in Wired magazine, MIT Tech Review, and Popular Science. He was a co-founder and co-chair of six NASA/DoD Conferences on Evolvable Hardware, and serves as an Associate Editor of IEEE Transactions on Evolutionary Computation.

Takahide Inoue, Berkeley / CITRIS “Opinion Space: Looking Beyond EDA/ Semiconductor”
Consistent and swearing efforts of semiconductor/EDA community more than 4 decades have developed many innovative IT based services especially last ten years. Now it may be good time for us to get benefit from new favorite such as Social Media since we are in hard time to find our lives in Beyond Semiconductor/EDA era. Social Media has tremendous potential for innovation and problem solving, but existing tools such as blogs, Twitter, wikis, can be quickly overwhelmed by the volume of responses and extreme viewpoints. “Opinion Space” is a new social media technology designed to help communities exchange ideas and suggestions about the issues, policies, and products they are passionate about. Opinion Space incorporates techniques from deliberative polling, collaborative filtering, and multidimensional visualization and introduces an intuitive graphical “map” that displays activity, patterns, trends, and insights as they emerge. A version of “Opinion Space” is being used by the U.S. State Department to collect ideas and suggestions on key foreign policy questions. See http://www.state.gov/opinionspace/. In this talk speaker will introduce “Opinion Space” with some live demo and is willing to discuss a project for “Looking Beyond Semiconductor/EDA” with the technology.
Takahide Inoue is a long time advocate of EECS at Berkeley and has been Special Research Advisor in CITRIS (Center for IT Research in the Interest of Society) since its inception in 2001. The role of Takahide Inoue in CITRIS is to advise the institute to be the prominent model of international Academia-Industry -Government collaboration in the interest of Society in 21st century. Takahide is one of the original members of CANDE before creation of ICCAD. From 1965 to 1998, he had been a member of Sony Corporation mostly on its semiconductor business unit where he developed various devices for Sony products such as world first IC radio, TV, VCR and CD audio and also EDA tools. Since 1991 he became Senior Vice President of Sony Corp. of America, SEMA in San Jose from 1991 to 1998. He received B.S in Electrical Engineering from Keio University and MBA from Northeastern University.

Dinner Keynote: Anirudh Devgan, Magma, Analog-Mixed Signal: The Next EDA Frontier

Analog circuits are designed in fundamentally different ways than their counterparts in the digital domain. However, two major trends have made analog and digital circuits mix and co-exist. First, high-performance analog circuits use digital parts and vice versa. Second, the desire for new features, ease of use and reducing integration costs brings together more digital, analog and RF circuits in one die. This convergence of circuits creates a significant need for analog and digital design automation to also unify. Furthermore, the time-to-market requirements of current analog, mixed-signal designs requires a fundamentally new approach from EDA. In this talk we describe EDA challenges and solutions to this critical problem. With ongoing commoditization of regular digital EDA tools, the real action in EDA is in analog, mixed signal design.

Anirudh Devgan serves as the General Manager and Corporate Vice President of Magma’s Custom Design Business unit. Devgan joined Magma in 2005 and manages Magma’s Custom Design Business Unit, responsible for FineSim SPICE and FineSim Pro circuit simulation products; SiliconSmart library characterization; Quartz DRC and Quartz LVS physical verification products; and the Titan analog/mixed-signal products. He spent 12 years at IBM in various management and technical positions at IBM Thomas J. Watson Research Center, IBM Server Division, IBM Microelectronics Division and IBM Austin Research Lab. Devgan, named an IEEE Fellow in 2006, was the recipient of DAC’s Best Paper Award in 2005, the IEEE William J. McCalla Best Paper Award in 2003, IBM Microelectronics Division’s Excellence Award in 2001, the 2000 IBM Corporate Award, and the IBM Outstanding Innovation Award and IBM Outstanding Research Accomplishment Award, both in 1999. He has served on program committees for various international conferences including DAC, ICCAD, ASP-DAC, VLSI Design and ISQED. Devgan has published more than 70 research papers and has 24 U.S. patents on various aspects of electronic design automation and circuit design. Devgan received a B. Tech. degree in electrical engineering from Indian Institute of Technology, Delhi, and M.S. & Ph.D. degrees in electrical and computer engineering from Carnegie Mellon University.

Automatic Security
Miodrag Potkonjak, UCLA, “Impossible problems caused by simple solutions and simple solutions for impossible problems”
Is it possible to design trusted ICs using untrusted tools? How can one remotely operate an IC while maintaining the ability to verify that produced results were actually created at a particular time and location? How can we place designers in complete control of remote IC fabrication? How can we prevent reverse engineering of an IC? Surprisingly, a few simple tricks, often in conjunction with deep submicron phenomena such as process variation, rapid thermal alternations, strong supply voltage dependencies, and aging, can be used to solve these and many other impossible security problems in elegant ways.We will also discuss hardware Trojans (HTs) that emerged as a potentially serious security threat. We summarize current threats and techniques to detect them then provide two contradictory proofs: one that any HT can be easily detected and one that there is an undetectable HT. Which proof is correct depends on which assumptions we accept.
Miodrag Potkonjak received his Ph.D. degree in EE and CS from Berkeley in 1991. He currently is a professor in the UCLA CS Department. He created the first watermarking, fingerprinting, metering techniques for integrated circuits, and for remote trusted sensing and trusted synthesis and compilation using untrusted tools.

Robert Lucas, USC Information Sciences Institute, “Imaging Integrated Circuits with 3D X-Ray Microscopy”
X-rays can be used to non-destructively create images of the metal features of a modern integrated circuit. Tomographic reconstruction from these images then yields a three-dimensional representation of the wires and vias, at a resolution today of 30 nm. This talk will describe the state-of-the-art of X-ray microscopy, present recent work to automate the process of imaging chips larger than the field of view of an X-ray microscope, and then extracting the various layers of the design.
Dr. Robert F. Lucas is the Director of the Computational Sciences Division of the University of Southern California’s Information Sciences Institute (ISI). There he manages research in computer architecture, VLSI, compilers and other software tools. Prior to joining ISI, he was the Head of the High Performance Computing Research Department in the National Energy Research Scientific Computing Center (NERSC) at Lawrence Berkeley National Laboratory. There he oversaw work in scientific data management, visualization, numerical algorithms, and scientific applications. Prior to joining NERSC, Dr. Lucas was the Deputy Director of DARPA’s Information Technology Office. He also served as DARPA’s Program Manager for Scalable Computing Systems and Data-Intensive Computing. From 1988 to 1998 he was a member of the research staff of the Institute for Defense Analyses, Center for Computing Sciences. From 1979 to 1984 he was a member of the Technical Staff of the Hughes Aircraft Company. Dr. Lucas received his BS, MS, and PhD degrees in Electrical Engineering from Stanford University in 1980, 1983, and 1988 respectively.

Krishna Sampigethaya, Boeing Research and Technology “Cyber Physical Systems Security”
This talk will present a background overview of what is now called the cyber-physical systems and present the set of security challenges that are faced by such systems. Talk will also identify what challenges are commonly faced as well as those that are unique to such systems. While the space of attacks on a distributed system can be large, we will present the need for new approaches and illustrate this with examples from aviation and consensus protocols.

Gang Qu, Maryland “Role of Hardware in Security and a Case Study on PUF”
Despite its own security and trust problems, hardware is playing a more and more important role in security. We will briefly demonstrate many security applications that rely on hardware. Then we will focus our discussion on the silicon physical unclonable function with emphasis on several practical techniques to improve its hardware utilization.
Gang Qu received his Ph.D. in Computer Science from UCLA in 2000 and as been with the University of Maryland since then. He is currently Associate Professor in the Electrical and Computer Engineering Department and the Institute for Systems Research. Dr. Qu works on the energy efficient design of computing devices and hardware related security and trust problems. He is the co-founder of the Maryland Embedded System Research Lab and a member of the Maryland Cybersecurity Center.