IEEE Circuits and Systems Society

IEEE Circuits and Systems Magazine – [Front Cover]

IEEE Circuits and Systems Society — Mon, 07 May 2012 09:02:42 +0000

Date of Publication: First Quarter 2012 Volume: 12 , Issue:

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IEEE Circuits and Systems Society — Thu, 03 May 2012 15:32:15 +0000

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IEEE Circuits and Systems Society — Tue, 01 May 2012 00:00:00 +0000

Two-Level Hardware Function Evaluation Based on Correction of Normalized Piecewise Difference Functions

IEEE Circuits and Systems Society — Tue, 01 May 2012 00:00:00 +0000

A new function-evaluation algorithm is presented using a two-level approximation scheme. In the first level, piecewise degree-one polynomial is used for initial approximation to obtain the so-called normalized difference functions that are similar in shape. Then, a shared normalized difference function is computed to achieve the target precision in the second level of refined approximation. We also perform the error analysis and bit-width optimization with two different design goals: area optimization and ROM optimization. Experimental results show that the proposed ROM-optimized architecture, when used in the multifunction evaluator for computing several elementary arithmetic functions on the same hardware, has significant area saving compared to previous approaches.

IEEE Transactions on Circuits and Systems—II: Express Briefs information for authors

IEEE Circuits and Systems Society — Tue, 01 May 2012 00:00:00 +0000

An Efficient DPA Countermeasure With Randomized Montgomery Operations for DF-ECC Processor

IEEE Circuits and Systems Society — Tue, 01 May 2012 00:00:00 +0000

Nowadays, differential power-analysis (DPA) attacks are a serious threat for cryptographic systems due to the inherent existence of data-dependent power consumption. Hiding power consumption of encryption circuit or applying key-blinded techniques can increase the security against DPA attacks, but they result in a large overhead for hardware cost, execution time, and energy dissipation. In this brief, a new DPA countermeasure performing all field operations in a randomized Montgomery domain is proposed to eliminate the correlation between target and reference power traces. After implemented in 90-nm CMOS process, our protected 521-bit dual-field elliptic curve (EC) cryptographic processor can perform one EC scalar multiplication in 8.08 ms over $GF(p_{521})$ and 4.65 ms over $GF(2^{409})$, respectively, with 4.3% area and 5.2% power overhead. Experiments from a field-programmable gate array evaluation board demonstrate that the private key of unprotected device will be revealed within $10^{3}$ power traces, whereas the same attacks on our proposal cannot successfully extract the key value even after $10^{6}$ measurements.

ISCAS 2013

IEEE Circuits and Systems Society — Tue, 01 May 2012 00:00:00 +0000

A 3.1–4.8-GHz IR-UWB All-Digital Pulse Generator With Variable Channel Selection in 0.13-$muhbox{m}$ CMOS Technology

IEEE Circuits and Systems Society — Tue, 01 May 2012 00:00:00 +0000

An all-digital pulse generator in a standard 0.13-$muhbox{m}$ CMOS technology for communication systems using an impulse radio ultrawideband signal is presented. A delay-line-based architecture utilizing only static logic gates for pulse generation with low-power characteristic is proposed in this brief. The center frequency and the fixed bandwidth of 500 MHz of the output signal can be digitally controlled to cover three channels in the low band of UWB spectrum. Delay-based binary phase shift keying and pulse position modulation schemes are exploited at the same time to modulate transmitted signals with further improvement in spectrum characteristics. The total energy consumption is 48 pJ/pulse at 1.2-V supply voltage without static bias currents.

High-Efficiency Differential-Chaos-Shift-Keying Scheme for Chaos-Based Noncoherent Communication

IEEE Circuits and Systems Society — Tue, 01 May 2012 00:00:00 +0000

In this brief, a new noncoherent chaos-based communication scheme, named high-efficiency differential chaos shift keying (DCSK) (HE-DCSK), is proposed. By recycling each reference sample in DCSK, 2 bits of data can be carried in one data-modulated sample sequence, which offers our scheme double bandwidth efficiency and nonrepeated transmitted signal less prone to interception in comparison to DCSK. The bit-error performance of the proposed scheme is studied analytically based on Gaussian approximation for discrete-time implementations. Simulations in additive-white-Gaussian-noise channel are performed and compared with DCSK and correlation delay shift keying (CDSK) schemes. Results show that the bit-error rate performance of HE-DCSK can always outperform CDSK and be even better than DCSK with typical spreading factors and at reasonable $E_{b}/N_{0}$ levels.

Clock-Phase-Noise-Induced TX Leakage Estimation of a Baseband Wireless Transmitter DAC

IEEE Circuits and Systems Society — Tue, 01 May 2012 00:00:00 +0000

In many wireless systems, the transmit (TX) signal could leak to the receiver input through the antenna duplexer, and this leakage could raise the noise level in the receive (RX) band. Therefore, it is important to be able to accurately predict the noise spectrum that leaks into the RX band from a TX digital-to-analog converter (DAC) in order to optimize the noise performance. This study analyzes the DAC output noise that is caused by the phase noise of the DAC clock. First, a closed-form equation is derived to account for both the phase noise and noise aliasing. Then, the proposed TX leakage prediction in the RX band is verified with both simulation and measurement. A clear understanding of the relationship between the clock phase noise and the DAC output noise spectrum could enable both the DAC and phase-locked loop designs to be optimized for the lowest RX band noise performance with low cost and power consumption at the same time.

IEEE Circuits and Systems Society

IEEE Circuits and Systems Magazine – [Front Cover]

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Two-Level Hardware Function Evaluation Based on Correction of Normalized Piecewise Difference Functions

IEEE Transactions on Circuits and Systems—II: Express Briefs information for authors

An Efficient DPA Countermeasure With Randomized Montgomery Operations for DF-ECC Processor

ISCAS 2013

A 3.1–4.8-GHz IR-UWB All-Digital Pulse Generator With Variable Channel Selection in 0.13-$muhbox{m}$ CMOS Technology

High-Efficiency Differential-Chaos-Shift-Keying Scheme for Chaos-Based Noncoherent Communication

Clock-Phase-Noise-Induced TX Leakage Estimation of a Baseband Wireless Transmitter DAC