Volume 63 | Issue 12

The theory, analysis,(computer aided) design, and practical implementation of circuits, and the application of circuit theoretic techniques to systems and to signal processing. Only full papers submissions are accepted.

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Editor

Dr. Andreas Demosthenous
Editor in Chief - 2016 - 2017
Department of Electronic and Electrical Engineering
University College London
a.demosthenous@ucl.ac.uk

Deputy Editor-in-Chief
Dr. Eduardo A. B. da Silva
Department of Electronics
Universidade Federal do Rio de Janeiro

Articles

This paper presents a 5-GS/s 12-way 10-b time-interleaved successive approximation register (SAR) ADC for direct sampling receivers. Proper signal and clock distribution along the multiple channels are utilized to mitigate interchannel bandwidth and timing mismatches. A digitally assisted calibration is introduced to remove the interchannel offset, gain, and timing mismatch. The T-type... Read more on IEEE Xplore

This paper presents a low-power built-in self-test system to compensate for mismatch and variations in CMOS IC. The system is designed and compiled on a low-power field programmable analog array (FPAA) fabricated on a 350-nm CMOS process. A second-order bandpass filter is used as a device under test. A set of 12 parallel filter banks are compiled on three different FPAA chips and compensated for... Read more on IEEE Xplore

The postmatching topology is an effective approach for broadening the bandwidth of a Doherty power amplifier (DPA). Its efficiency can be enhanced using a second-harmonic short-circuit network (SHSN), but at the expense of bandwidth. In this paper, the SHSNs with mutual coupling are proposed to achieve efficiency enhancement without sacrificing bandwidth. A broadband Doherty amplifier was... Read more on IEEE Xplore

This paper presents an adaptive QR decomposition (QRD) processor for five-band carrier-aggregated Long Term Evolution-Advanced downlinks. The design uses time and frequency correlation properties of wireless channels to reduce QRD computations while maintaining an uncoded bit error rate loss below 1 dB. An analysis on the performance of a linear interpolating QRD is presented, and optimum... Read more on IEEE Xplore

In this paper, we use synchronization to reduce phase-locked loop (PLL) phase noise and improve its locking behavior with an attenuated reference signal injection (RI) into a voltage-controlled CMOS delay-line ring-type oscillator. The transient and steady-state behavior of the PLL-RI are described by a nonlinear differential equation, which is further studied by the phase-plane method. The... Read more on IEEE Xplore