Volume 63 | Issue 12

The theory, analysis, (computer aided) design, and practical implementation of circuits, and the application of circuit theoretic techniques to systems and to signal processing. Only brief papers (maximum length less or equal five pages in standard IEEE Transactions submissions ) are considered for possible publication.

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Dr. Chi K. Michael Tse
Editor in Chief - 2016 - 2017
Department of Electronic Engineering
Hong Kong Polytechnic University

Dr. Jose M. de la Rosa
Deputy Editor-in-Chief
Institute of Microelectronics of Seville, MMSE-CNM


The well-known three-moduli set (<inline-formula> <tex-math notation="LaTeX">$ {2}^{ {n}} {+1}$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$ {2}^{ {n}}$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$ {2}^{ {n}} {-} {1}$ </tex-math></inline-... Read more on IEEE Xplore

This brief presents a hardware-efficient logarithm circuit design based on a novel discontinuous piecewise linear approximation method. Hardware synthesis results targeted for a commercial application specific integrated circuit cell library and field-programmable gate array show the practicality of the proposed design. A new figure of merit that combines error, area, time, and power is... Read more on IEEE Xplore

This brief presents a three-way Doherty power amplifier (DPA) with a symmetric structure in terms of the output power capacities between the carrier and peaking amplifiers for high efficiency and linearity. Based on the analysis for the efficiency peak at the output power back-off, a symmetric structure was adopted to have higher overall efficiency for the modulated signal. Through the optimized... Read more on IEEE Xplore

This brief presents a novel biquadratic cell (biquad) based on the flipped-source-follower (FSF) circuit. The main idea is to exploit the FSF circuit as a basic building block for a low-pass second-order filter, taking advantage of its well-known strengths, like low-output impedance, low-noise, large in-band linearity, and low power. Thanks to the very essential FSF circuit, the resulting biquad... Read more on IEEE Xplore

This brief presents a low-voltage folded-switching mixer in 65-nm CMOS process. A modified complimentary common gate pair is utilized as the input transconductance stage, where a transformer is subtly applied for chip size reduction. Benefitted from the current reuse, the pMOS transistor not only works for radio frequency (RF) signal amplification, but also acts as the current bleeding path. This... Read more on IEEE Xplore