Volume 24 | Issue 12

Includes all major aspects of the design and implementation of VLSI/ULSI and microelectronic systems. Topics of special interest include: systems specifications, design and partitioning, high performance computing and communication systems, neural networks, wafer-scale integration and multichip module systems and their applications.

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Editor

Professor Krishnendu Chakrabarty
Dept. of Elect. Eng.
Duke University
Durham, NC 27708
Krish@duke.edu

Articles

Presents the table of contents for this issue of this publication.

Provides a listing of current staff, committee members and society officers.

System accelerators (ACCs) improve performance and break power and utilization walls. They can be implemented by fixed-function hard macros or reconfigurable logic such as field-programmable gate arrays (FPGAs). For systems running various applications, dynamic reconfigurable ACCs offer a very attractive feature; however, the reconfiguration time is an unavoidable overhead. This paper proposes... Read more on IEEE Xplore

Timing error predictors have a strong potential to reduce the worst case timing margins by monitoring timing slack of a design. However, these timing error predictors incur substantial amount of silicon area and power which limit the overall benefits in the system level. This paper presents a low overhead warning flip-flop (FF), which predicts setup time violations. It consists of a delay buffer... Read more on IEEE Xplore

A common mechanism to ensure cache coherence is to issue snoop requests to all processors to check for the presence of cached data. Since most of snoop requests result in misses in caches and waste a lot of power, snoop filters are widely used to filter out unnecessary snoop requests to reduce power consumption. However, snoop filters also suffer from the similar problem that the false positive... Read more on IEEE Xplore