Volume 24 | Issue 12

Includes all major aspects of the design and implementation of VLSI/ULSI and microelectronic systems. Topics of special interest include: systems specifications, design and partitioning, high performance computing and communication systems, neural networks, wafer-scale integration and multichip module systems and their applications.

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Editor

Professor Krishnendu Chakrabarty
Dept. of Elect. Eng.
Duke University
Durham, NC 27708
Krish@duke.edu

Articles

Continuous shrinking of the size of CMOS technology leads to extremely fast devices, but the resulting interconnect structures impose so many parasitic effects that the advantage of extremely scaled and ultrahigh-speed transistors would be completely overshadowed if appropriate remedial steps are not taken. This requires an accurate and efficient estimation of interconnect parasitics and analysis... Read more on IEEE Xplore

This paper presents an automatic resistive random access memory (ReRAM) SPICE model generator, which enables fast ReRAM circuit evaluation with standard SPICE. Our model generator automatically produces SPICE models of ReRAM devices and selectors from the measured I-V data to reduce too much time consumption in manual model development for ReRAM devices and simulation of the target ReRAM circuits... Read more on IEEE Xplore

The 3-D integration helps improve performance and density of electronic systems. However, since electrical and thermal performance for 3-D integration is related to each other, their codesign is required. Machine learning, a promising approach in artificial intelligence, has recently shown promise for addressing engineering optimization problems. In this paper, we apply machine learning for the... Read more on IEEE Xplore

We propose an approach called buffered compares, a less-invasive processing-in-memory solution that can be used with existing processor memory interfaces such as DDR3/4 with minimal changes. The approach is based on the observation that multibank architecture, a key feature of modern main memory DRAM devices, can be used to provide huge internal bandwidth without any major modification. We place... Read more on IEEE Xplore

The objective of post-silicon validation is to identify design errors that remain undetected after pre-silicon verification and, therefore, manifest themselves in the silicon prototypes. These errors are often associated with the subtle interactions between the electrical states of the systems and commonly manifest in the logic domain as bit-flips in flip-flops. They occur under unique operating... Read more on IEEE Xplore