Volume 24 | Issue 12

Includes all major aspects of the design and implementation of VLSI/ULSI and microelectronic systems. Topics of special interest include: systems specifications, design and partitioning, high performance computing and communication systems, neural networks, wafer-scale integration and multichip module systems and their applications.

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Editor

Professor Krishnendu Chakrabarty
Dept. of Elect. Eng.
Duke University
Durham, NC 27708
Krish@duke.edu

Articles

Presents the table of contents for this issue of the publication.

Provides a listing of the editorial board, current staff, committee members and society officers.

We present, in this paper, a new 10T static random access memory cell having single ended decoupled read-bitline (RBL) with a 4T read port for low power operation and leakage reduction. The RBL is precharged at half the cell's supply voltage, and is allowed to charge and discharge according to the stored data bit. An inverter, driven by the complementary data node (QB), connects the RBL to... Read more on IEEE Xplore

Spin-transfer torque magnetoresistance random access memory is a major contender for static random access memory replacement in embedded caches at advanced fin field effect transistor nodes. It suffers, however, from the low resistance difference between the bistable states of the magnetic tunnel junction (MTJ). Variability on MTJ resistance and access transistors makes reliable read-out even... Read more on IEEE Xplore

A framebuffer memory is data storage for the displayed image, which is one of the major power consumers in display systems. This paper proposes a power reduction technique for the on-chip framebuffer cache (FBC) performing a compressed image data management. The proposed architecture stores the compressed image data in the on-chip FBC, and the display controller decompresses the image data on the... Read more on IEEE Xplore