October 2018, Volume 65, Issue 10

Multi-Rate DEM With Mismatch-Noise Cancellation for DCOs in Digital PLLs
E. Alvarez-Fontecilla, C. Venerus, and I. Galton

Power and Conjugately Matched High Band UWB Power Amplifier
M. M. Mili´cevi´c, B. S. Milinkovi´c, D. N. Gruji´c, and L. V. Saranovac

A Seven-Octave Broadband LNA MMIC Using Bandwidth Extension Techniques and Improved Active Load
J. Hu, K. Ma, S. Mou, and F. Meng

A Low-Voltage Low-Phase-Noise 25-GHz Two-Tank Transformer-Feedback VCO
S. Guo, P. Gui, T. Liu, T. Zhang, T. Xi, G. Wu, Y. Fan, and M. Morgan

A 2.5-GHz CMOS Full-Duplex Front-End for Asymmetric Data Networks
A. Kumar and S. Aniruddhan

A 0.8–4-GHz Software-Defined Radio Receiver With Improved Harmonic Rejection Through Non-Overlapped Clocking
A. Bazrafshan, M. Taherzadeh-Sani, and F. Nabki

A Wideband Inductorless dB-Linear Automatic Gain Control Amplifier Using a Single-Branch Negative Exponential Generator for Wireline Applications
L. Kong, Y. Chen, C. C. Boon, P.-I. Mak, and R. P. Martins

Degradation of Alias Rejection in Continuous-Time Delta–Sigma Modulators by Weak Loop-Filter Nonlinearities
S. Manivannan and S. Pavan

Analysis and Modeling of Chopping Phase Non-Overlap in Continuous-Time ΔΣ Modulators
K. Singh

Area-Efficient Time-Shared Digital-to-Analog Converter With Dual Sampling for AMOLED Column Driver IC’s
T.-J. An, M.-S. Hwang, W.-J. Choe, G.-C. Ahn, and S.-H. Lee

Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems
H. Okuhara, A. B. Ahmed, and H. Amano

Efficient ASK Data and Power Transmission by the Class-E With a Switchable Tuned Network
M. L. Navaii, H. Sadjedi, and A. Sarrafzadeh

Generalized Analysis of High-Order Switch-RC N-Path Mixers/Filters Using the Adjoint Network
S. Pavan and E. Klumperink

A Design Method for Nested MASH-SQ Hybrid Divider Controllers for Fractional-N Frequency Synthesizers
D. Mai and M. P. Kennedy

An Area Efficient 1024-Point Low Power Radix-22 FFT Processor With Feed-Forward Multiple Delay Commutators
N. L. Ba and T. T.-H. Kim

ASNI: Attenuated Signature Noise Injection for Low-Overhead Power Side-Channel Attack Immunity
D. Das, S. Maity, S. B. Nasir, S. Ghosh, A. Raychowdhury, and S. Sen

A Modular and Reconfigurable Pipeline Architecture for Learning Vector Quantization
X. Zhang, F. An, L. Chen, I. Ishii, and H. J. Mattausch

Pentavariate Vmin Analysis of a Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write and Divided Bit-Line Read
S. Gupta, K. Gupta, and N. Pandey

Time-Based Sensing for Reference-Less and Robust Read in STT-MRAM Memories
Q.-K. Trinh, S. Ruocco, and M. Alioto

A Low-Complexity Hardware for Deterministic Compressive Sensing Reconstruction
M. Fardad, S. M. Sayedi, and E. Yazdian

A Fast and Power-Efficient Hardware Architecture for Visual Feature Detection in Affine-SIFT
P. Ouyang, S. Yin, L. Liu, Y. Zhang, W. Zhao, and S. Wei

Superior Execution Time Design of a Space/Spatial-Frequency Optimal Filter for Highly Nonstationary 2D FM Signal Estimation
V. N. Ivanovi´c and N. R. Brnovi´c

Random Fourier Filters Under Maximum Correntropy Criterion
S. Wang, L. Dang, B. Chen, S. Duan, L. Wang, and C. K. Tse

Data-Driven Filtering for Nonlinear Systems With Bounded Noises and Quantized Measurements
Y. Xia, D. Yu, L. Li, H. Yang, and W. Xie

A 1.4-mW 14-MHz MEMS Oscillator Based on a Differential Adjustable-Bandwidth Transimpedance Amplifier and Piezoelectric Disk Resonator
A. Bouchami, M. Y. Elsayed, and F. Nabki

A Study on the Design Parameters for MEMS Oscillators Incorporating Nonlinearities
M.-H. Li, C.-Y. Chen, and S.-S. Li

Accurate Shielded Interconnect Delay Estimation by Reconfigurable Ring Oscillator
E. Sarfati, B. Frankel, Y. Birk, and S. Wimer

A Built-In Self-Test and In Situ Analog Circuit Optimization Platform
S. Lee, C. Shi, J. Wang, A. Sanabria, H. Osman, J. Hu, and E. Sánchez-Sinencio

X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design
R. Liu, P.-Y. Chen, X. Peng, and S. Yu

A Simple Piecewise Model of Reset/Set Transitions in Bipolar ReRAM Memristive Devices
M. M. Al Chawa, C. de Benito, and R. Picos

Finite-Time H∞ State Estimation for Discrete Time-Delayed Genetic Regulatory Networks Under Stochastic Communication Protocols  
X. Wan, Z. Wang, Q.-L. Han, and M. Wu

Fault Detection for Linear Discrete Time-Varying Systems With Multiplicative Noise: The Finite-Horizon Case
Y. Li, H. R. Karimi, M. Zhong, S. X. Ding, and S. Liu

Event-Based Consensus for a Class of Nonlinear Multi-Agent Systems With Sequentially Connected Topology
Y. Cui, Y. Liu, W. Zhang, and F. E. Alsaadi

Reliable Control of Fuzzy Singularly Perturbed Systems and Its Application to Electronic Circuits
Y. Wang, P. Shi, and H. Yan

Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders
H. Yueksel, M. Braendli, A. Burg, G. Cherubini, R. D. Cideciyan, P. A. Francese, S. Furrer, M. Kossel, L. Kull, D. Luu, C. Menolfi, T. Morf, and T. Toifl

An Energy-Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder Architecture
N. Prasad, I. Chakrabarti, and S. Chattopadhyay

Fully-Parallel Stochastic Decoder for Rate Compatible Modulation
F. Lu, Y. Dong, and C. W. Chen

A 60 mV Input Voltage, Process Tolerant Start-Up System for Thermoelectric Energy Harvesting
M. Dezyani, H. Ghafoorifard, S. Sheikhaei, and W. A. Serdijn

A Fully Integrated Low-Dropout Regulator With Differentiator-Based Active Zero Compensation
S. Bu, K. N. Leung, Y. Lu, J. Guo, and Y. Zheng

Time-Domain Characterization of Digitized PWM Inverter With Dead-Time Effect
M. Kumar