December 2018, Volume 65, Issue 12

An Oversampling Stochastic ADC Using VCO-Based Quantizers
Hyuk Sun; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon

A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems
Nikola Ivanisevic; Saul Rodriguez; Ana Rusu

Miniaturized Resonator and Bandpass Filter for Silicon-Based Monolithic Microwave and Millimeter-Wave Integrated Circuits
He Zhu; Yang Yang; Xi Zhu; Yichuang Sun; Sai-Wai Wong

Differential Capacitive Readout Circuit Using Oversampling Successive Approximation Technique
Longjie Zhong; Xinquan Lai; Hongjiang Song; Donglai Xu

A High-Precision Resistor-Less CMOS Compensated Bandgap Reference Based on Successive Voltage-Step Compensation
Xin Ming; Li Hu; Yang-Li Xin; Xuan Zhang; Di Gao; Bo Zhang

Statistics-Based Digital Background Calibration of Residue Amplifier Nonlinearity in Pipelined ADCs
Hamidreza Mafi; Mostafa Yargholi; Mohammad Yavari

Power Bounds and Energy Efficiency in IncrementalΔΣAnalog-to-Digital Converters
Saqib Mohamad; Jie Yuan; Amine Bermak

Loop-Filter Design and Analysis for Delta-Sigma Modulators and Oversampled IIR Filters
Matthew Sienko

Distortion Contribution Analysis With the Best Linear Approximation
Adam Cooman; Piet Bronders; Dries Peumans; Gerd Vandersteen; Yves Rolain

Amplifier Design for Specified Frequency Response Profiles Using Nullors–Hearing Aids, a Case Study
Reza Hashemian

Second-Order Equivalent Circuits for the Design of Doubly-Tuned Transformer Matching Networks
Andrea Mazzanti; Andrea Bevilacqua

Approximate Multipliers Based on New Approximate Compressors
Darjn Esposito; Antonio Giuseppe Maria Strollo; Ettore Napoli; Davide De Caro; Nicola Petra

CORDIC-Based Architecture for Computing Nth Root and Its Implementation
Yuanyong Luo; Yuxuan Wang; Huaqing Sun; Yi Zha; Zhongfeng Wang; Hongbing Pan

Energy-Efficient Convolution Architecture Based on Rescheduled Dataflow
Jihyuck Jo; Suchang Kim; In-Cheol Park

Gain-Cell Embedded DRAM-Based Physical Unclonable Function
Robert Giterman; Yoav Weizman; Adam Teman

X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories
Amogh Agrawal; Akhilesh Jaiswal; Chankyu Lee; Kaushik Roy

Modeling Circuits With Arbitrary Topologies and Active Linear Multiports Using Wave Digital Filters
Kurt James Werner; Alberto Bernardini; Julius O. Smith; Augusto Sarti

Efficient Shift-Add Implementation of FIR Filters Using Variable Partition Hybrid Form Structures
Dwaipayan Ray; Nithin V. George; Pramod Kumar Meher

IMAGING: In-Memory AlGorithms for Image processiNG
Ameer Haj-Ali; Rotem Ben-Hur; Nimrod Wald; Ronny Ronen; Shahar Kvatinsky

Analysis and Design of Nonlinear Circuits With a Self-Consistent Carleman Linearization
Harry Weber; Wolfgang Mathis

Energy-Efficient Neural Network Acceleration in the Presence of Bit-Level Memory Errors
Sung Kim; Patrick Howe; Thierry Moreau; Armin Alaghi; Luis Ceze; Visvesh S. Sathe

An Accelerated LIF Neuronal Network Array for a Large-Scale Mixed-Signal Neuromorphic Architecture
Syed Ahmed Aamir; Yannik Stradmann; Paul Müller; Christian Pehle; Andreas Hartel; Andreas Grübl; Johannes Schemmel; Karlheinz Meier

Synthesis of Ternary Logic Circuits Using 2:1 Multiplexers
Chetan Vudadha; Ajay Surya; Saurabh Agrawal; M. B. Srinivas

QBF-Based Post-Silicon Debug of Speed-Paths Under Timing Variations
Bijan Alizadeh; Mehdi Shakeri

Finite-Time Bipartite Consensus for Multi-Agent Systems on Directed Signed Networks
He Wang; Wenwu Yu; Guanghui Wen; Guanrong Chen

Lossless Systems Storage Function: New Results and Numerically Stable and Non-Iterative Computational Methods
Ashish Kothyari; Cornelis Praagman; Madhu N. Belur

Exponential Consensus of Multiagent Systems With Lipschitz Nonlinearities Using Sampled-Data Information
Junjie Fu; Guanghui Wen; Wenwu Yu; Tingwen Huang; Jinde Cao

A Discrete-Time RF Signal-Processing Technique for Blocker-Tolerant Receivers With Wide Instantaneous Bandwidth
Mohammad Ghadiri-Sadrabadi; Joseph C. Bardin

A Novel Digital-Intensive Hybrid Polar-I/Q RF Transmitter Architecture
Tobias Buckel; Peter Preyler; Alexander Klinkan; Damir Hamidovic; Christoph Preissl; Thomas Mayer; Stefan Tertinek; Siegfried Brandstaetter; Christian Wicpalek; Andreas Springer; Robert Weigel

Advanced Bit Flip Concatenates BCH Code Demonstrates 0.93% Correctable BER and Faster Decoding on (36 864, 32 768) Emerging Memories
Sheyang Ning

A Multi-Kernel Multi-Code Polar Decoder Architecture
Gabriele Coppolino; Carlo Condo; Guido Masera; Warren J. Gross

A Double-Isolated DC–DC Converter Based on Integrated LC Resonant Barriers
Nunzio Greco; Alessandro Parisi; Pierpaolo Lombardo; Nunzio Spina; Egidio Ragonese; Giuseppe Palmisano

A Splitting Frequencies-Based Wireless Power and Information Simultaneous Transfer Method
Jin-Guk Kim; Guo Wei; Man-Ho Kim; Hyok-Su Ryo; Phyong-Chol Ri; Chunbo Zhu