May 2017, Volume 64, Issue 5

Guest Editorial 

Special Section on the 2016 IEEE Latin American Symposium on Circuits and Systems (LASCAS 2016)
P. M. Julián and L. Lovisolo

Special Section Papers 

Design and Experimental Evaluation of a Time-Interleaved ADC Calibration Algorithm for Application in High-Speed Communication Systems
B. T. Reyes, R. M. Sanchez, A. L. Pola, and M. R. Hueda

Hardware/Software Approach to Designing Low-Power RNS-Enhanced Arithmetic Units
P. Patronik and S. J. Piestrak

Single Bit Filtering Circuit Implemented in a System for the Generation of Colored Noise
E. Napoli, G. Castellano, D. De Caro, D. Esposito, N. Petra, and A. G. M. Strollo

Design of Efficient Multiplierless Modified Cosine-Based Comb Decimation Filters: Analysis and Implementation
G. Jovanovic Dolecek, J. R. Garcia Baez, and M. Laddomada

Implementation of Locally-Clocked XBM State Machines on FPGAs Using Synchronous CAD Tools
F. Tuyama De Faria Barbosa, D. L. De Oliveira, T. S. Curtinhas, L. de Abreu Faria, and J. F. De Souza Luciano

Regular Papers

Analysis and Design of VCO-Based Phase-Domain ΣΔ Modulators
U. Sönmez, F. Sebastiano, and K. A. A. Makinwa

A 1-V 5-MHz Bandwidth 68.3-dB SNDR Continuous-Time Delta-Sigma Modulator With a Feedback-Assisted Quantizer
C.-H. Weng, Y.-Y. Lin, and T.-H. Lin

An Ultra-Low Power 1.7-2.7 GHz Fractional-N Sub-Sampling Digital Frequency Synthesizer and Modulator for IoT Applications in 40 nm CMOS
Y.-H. Liu, J. van den Heuvel, T. Kuramochi, B. Busze, P. Mateman, V. K. Chillara, B. Wang, R. B. Staszewski, and K. Philips

A 95-dBA DR Digital Audio Class-D Amplifier Using a Calibrated Digital-to-Pulse Converter
C.-M. Chang and J.-T. Wu

A Low-Power Analog Adder and Driver Using a-IGZO TFTs
P. G. Bahubalindruni, V. G. Tavares, R. Martins, E. Fortunato, and P. Barquinha

A Generalized Combiner Synthesis Technique for Class-E Outphasing Transmitters
M. Özen, M. van der Heijden, M. Acar, R. Jos, and C. Fager

Microwave Characteristics of an Independently Biased 3-Stack InGaP/GaAs HBT Configuration
M. D. Luong, R. Ishikawa, Y. Takayama, and K. Honjo

Hardware Implementation Overhead of Switchable Matching Networks
E. L. Firrao, A.-J. Annema, F. E. van Vliet, and B. Nauta

A High-Speed and Ultra Low-Power Subthreshold Signal Level Shifter
E. Maghsoudloo, M. Rezaei, M. Sawan, and B. Gosselin

Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure
X. Tang, E. Giacomin, G. De Micheli, and P.-E. Gaillardon

Minimizing Coefficients Wordlength for Piecewise-Polynomial Hardware Function Evaluation With Exact or Faithful Rounding
D. De Caro, E. Napoli, D. Esposito, G. Castellano, N. Petra, and A. G. M. Strollo

Rakeness-Based Design of Low-Complexity Compressed Sensing
M. Mangia, F. Pareschi, V. Cambareri, R. Rovatti, and G. Setti

Fractional Hilbert Transform Sampling Method and Its Filter Bank Reconstruction
C.-C. Tseng and S.-L. Lee

A Study of Injection Locking in Dual-Band CMOS Frequency Dividers
A. Buonomo and A. Lo Schiavo

Stability of Power Control in Multiple Coexisting Wireless Networks: An L2 Small-Gain Perspective
R. Qian, Z. Duan, and Y. Qi

Discrete Adjoint Sensitivity Analysis of Hybrid Dynamical Systems With Switching
H. Zhang, S. Abhyankar, E. Constantinescu, and M. Anitescu

Joint Symbol and Chip Synchronization for a Burst-Mode-Communication Superregenerative MSK Receiver
A. López-Riera, F. del Águila-López, P. Palá-Schönwälder, J. Bonet-Dalmau, R. Giralt-Mas, and F. X. Moncunill-Geniz

First Principles Optimization of Opto-Electronic Communication Links
K. T. Settaluri, C. Lalau-Keraly, E. Yablonovitch, and V. Stojanovc