The goal of the Cellular Nanoscale Networks and Array Computing (CNNAC) Technical Committee is to foster research, development, education and industrial dissemination of knowledge relating to the emerging field of cellular dynamic computers and models briefly called CNN computing.
CNN (“cellular neural/nonlinear network”) computing is used as a generic terms for analog and logic (analogic) stored programmable array computers and models with a core of mainly locally interconnected dynamical systems. The activity is genuinely multidisciplinary, drawing upon knowledge and expertise from fields such as biology, physics and chemistry, in addition to areas more traditionally associated with the IEEE such as electrical and computer engineering, computer science and information technology.

Upcoming activities

(email the TC Secretary – – for more details)

Recent activities

Vision of the CNNAC TC

The vision of the CNNAC TC is to support and maintain the relevance of cellular nanoscale networks and array computing in CAS.
More specifically, executing on this vision requires accomplishing the following long term goals:

  1. Promote research activities in CNNAC and ensuring that mainstream engineering and industrial applications embrace this area of technology.
  2. Continue research activities in CNNAC including related areas such as
  3. Facilitate fertilization of ideas across disciplines such as biology, computer
    science, nanotechnology, massively multiprocessor computer architecture and system science.

The Technical Committee plans to accomplish these goals via the following action items.

  1. Organize workshops, special sessions and special journal issues and attract diverse IEEE members to contribute. In particular, we plan to continue organizing the biennial CNNA workshop and attracting participants from both industry and academia. Furthermore, we plan to coordinate the CNNA workshop with other relevant workshops such as the Memristor Symposium. Other plans include initiating a regular CNN summer school and a regular 3D integration workshop starting in 2011, possibly in collaboration with the Nano-Giga TC. In addition, we will continue to promote and organize at least one special session at each ISCAS and ECCTD, promoting special issues in IEEE journals on topics relevant to the TC and having members participating in various positions of the IEEE CAS, such as BoG and DLP.
  2. Leverage the expertise and experience of the TC members to define the direction of this area and identify future trends. Some possible new directions include locality dependent massive multicore/multiprocessor architectures and computing platforms, integration of non-homogenous and mixed-mode systems, implementation of neuromorphic and smart sensory hardware, computation for memristive networks, distributed memory organization and distributed algorithms.