Future research directions: where the field is going
The field in which the VSA-TC is currently active is certainly broad, and is expected to further broaden in the future. In particular, the VSA-TC field is expected to expand both at the bottom (wider range of potential technologies that will complement or eventually replace CMOS) and the top (more complex system). This is a consequence of expected technology breakthrough and exponentially increasing complexity at the same time.
At the bottom, novel techniques, models design methodologies and CAD tools will be needed to take full advantage of post-CMOS technologies and deal with the new challenges posed by them. At the top, it is foreseen that the Moore’s law will continue to be valid in a certain way, in the sense that the number of components within a system will exponentially increase (e.g., multi-core systems). This will require a stronger effort in taking advantage of massive parallelism to steadily increase the performance, as well as in devising design methodologies that permit to integrate, verify and test highly-complex and heterogenous systems, where CMOS technology is complemented by other technologies (like MEMS, sensors, bottom-up self-assembling technologies and so on). These new methodologies and techniques will have to stimulate a stronger impact of More-than-Moore technologies, so that the expected trends (performance, complexity, power, and so on) can be reached faster, or at least at the pace that is envisioned today.
The synergy between the “bottom” and the “top” (through appropriate models, methodologies and tools) will be key to keep the benefits obtained from scaling, and make technology advances worthwhile and profitable. Accordingly, the boundaries of the levels of abstraction will fade out, as a tighter link will be needed between adjacent levels of abstraction to face current and upcoming challenges.
Energy efficiency will be even a more critical issue, and will have to be addressed in a systematic way at all levels of abstraction. Adaptive schemes will be widely investigated to keep circuits and systems close to the desired optimum energy point under other constraints and conditions (workload, …). This will require the control of knobs (e.g., supply voltage) through on-chip blocks with a progressively finer granularity, which in turn will require a significant research effort to keep the overhead of these schemes low. From this perspective, the synergy between the “bottom” and the “top” will also be exploited in different on-line decided platform mapping options for the same I/O functionality, switching between different algorithms or accuracy decisions for the same SNR or BER functionality.
This increased complexity will pose formidable challenges in terms of intra- and inter-chip interconnects, which will have to sustainably grow in terms of performance and energy efficiency. 3D, optical and wireless inter-chip interconnects will play a major role in making inter-chip communications faster and more efficient. Due to the increased complexity, thermal issues will be even more critical than today, and the adoption of innovative inter-chip links will offer new challenges and opportunities. Design productivity will also be a topic that is expected to be of greater importance in future activities of the VSA-TC, which will require a wide research effort to build and consolidate a background in design-friendly techniques, methodologies and tools. A significant research effort will be devoted to the exploration of CAD tools targeting multiple objectives simultaneously (e.g., speed, power, area, functionality, reliability, testability, etc.)
Reliability will be a very critical concern that will have to be addressed at all levels of abstraction by introducing adaptive techniques and tuning, redundancy, error detection and correction. Among the aims envisioned for the activities of the VSA-TC, design techniques (from circuit to architecture and system), methodologies and CAD tools to build reliable systems with unreliable components will be important topics for the VSA-TC in the foreseeable future. To keep the overhead within reasonable limits, a hybrid design-time and run-time approach will have to be followed to allow handling and exploiting the very dynamic behavior present in modern systems. Moreover, our TC will strengthen the recent focus on the reduction and compensation of Process/Voltage/Temperature variations in fine geometry processes.
Main activities in the field of VSA-TC in the next 5-10 years
The expected expansion of the field in which the VSA-TC is involved will lead to new activities (which add to the current ones), some of which are described in the following. These activities will add to the more traditional topics in which the VSA-TC is currently involved:
– Exploration and early evaluation of post-CMOS technologies as replacement of CMOS in the context of practical applications, to direct research investments and effort to the right direction as early as possible.
– Pushing the boundary of energy consumption, enabling mass production of ultra-low power systems for recent and promising applications (biomedical in a broad sense, green electronics, ambient intelligence, wearable computing…). The goal is to enable the implementation of systems that operate at ultra-low power levels ( or even less, usually delivered by energy-scavenged devices), have the full capability to sense, process and communicate information, and meet design (power, performance, functionality, …) and market (cost, reliability, interoperability…) requirements.
– Aggressive voltage scaling with progressively finer granularity. Arithmetic precision (or output signal quality) will be treated as a further dimension of the design, being traded off with performance, energy and robustness in systems made up of unreliable components.
– Increased fault tolerance through error detection (correction) techniques with low area/power overhead.
– Simulation, verification, integration and testing of systems built with components based on heterogeneous technologies (e.g., MEMS, sensors, different CMOS technologies…), through innovative techniques and methodologies.
– Adaptive and reconfigurable circuits with high flexibility to fit a wide range of applications for energy-efficient high-speed computing.
– More systematic and effective techniques to reduce and counteract Process/Voltage/Temperature variations at fine geometry processes.
– Exploration of CAD tools for multiple simultaneous objectives (e.g., speed, power, area, functionality, reliability, testability, etc.).
– Real time and high performance/cloud computing.
– Circuit/system-level techniques, methodologies and tools to stimulate the adoption and the integration of More than Moore technologies, and boost the trends of performance, energy efficiency, functionality, degree of interaction with the external world, and so on.
– Adaptive mapping of different algorithms for the same functionality on the same die for improved energy efficiency for a wide range of conditions (e.g., workload).
An-Yeu (Andy) Wu (Past Chair)
Massimo Alioto (Past Chair)