Jitter Minimization in Digital PLLs with Mid-Rise TDCs

Authors: Luca Avallone; Michael Peter Kennedy; Saleh Karman; Carlo Samori; Salvatore Levantino

Introduction: “In modern communication systems, advanced CMOS processes can be applied in the all-digital implementation of the phase-locked loop (PLL). In particular, the phase detector is crucial in the all-digital PLL as it can detect any phase error and provide negative feedback control to adjust the oscillator.

The adoption of a time shift sign detector that outputs +1 or -1 introduces an extra quantization error and deteriorates its noise performance. Hence, our work provides an overview of the relationship between the number of phase detectors and the induced error,  paving the way for designing a high-performance digital PLL.”

------From Authors

For more informations visit IEEE Xplore.

Follow TCAS-1:

Linkedin: https://www.linkedin.com/company/ieee-transactions-on-circuits-and-systems-i/
Wechathttps://mp.weixin.qq.com/s/BZfCuOpuh4xfU76ep4lUdA
Facebook: https://www.facebook.com/IEEE-Transactions-on-Circuits-and-Systems-I-107925844105642/