Guest Editorial Special Issue on the 2021 ISICAS: A CAS Journal Track Symposium

Yajun Ha; Edoardo Bonizzoni


A 0.6-to-1.8V CMOS Current Reference With Near-100% Power Utilization

Luigi Fassio; Longyang Lin; Raffaele De Rose; Marco Lanuzza; Felice Crupi; Massimo Alioto


A Wideband Sliding Correlation Channel Sounder in 65 nm CMOS: Evaluation Board Performance

Dipankar Shakya; Ting Wu; Michael E. Knox; Theodore S. Rappaport


A Supply Voltage Noise Immunity Enhancement Design for High-Voltage Gate Driver IC Based on Bootstrap Circuit

Wookang Jin; Kunhee Cho


A 19–48.3-GHz 6th-Order Transformer-Based Injection-Locked Frequency Divider With 87.1% Locking Range in 40-nm CMOS

Junhua Zhu; Qiyao Jiang; Hamed Mosalam; Chenchang Zhan; Quan Pan


A 56-Gb/s PAM4 Receiver Analog Front-End With Fixed Peaking Frequency and Bandwidth in 40-nm CMOS

Zhenghao Li; Minzhe Tang; Taiyang Fan; Quan Pan


A 26GHz Fractional-N Digital Frequency Synthesizer Leveraging Noise Profiles of Three Functional Stages

Seongun Bae; Minseob Lee; Hwasuk Cho; Jae-Yoon Sim


64 dB Dynamic-Range 810 μW 90 MHz Fully-Differential Flipped-Source-Follower Analog Filter in 28nm-CMOS

Marcello De Matteis; Nicolas Galante; Federico Fary; Elia Vallicelli; Andrea Baschirotto


A 300mV-Supply, Sub-nW-Power Digital-Based Operational Transconductance Amplifier

Pedro Toledo; Paolo Crovetti; Hamilton Klimach; Sergio Bampi; Orazio Aiello; Massimo Alioto


NS-MD: Near-Sensor Motion Detection With Energy Harvesting Image Sensor for Always-On Visual Perception

Maimaiti Nazhamaiti; Han Xu; Zheyu Liu; Yixuan Chen; Qi Wei; Xing Wu; Fei Qiao


High-Speed Dynamic Level Shifter for High-Side Bootstrapped Gate Driver in High-Voltage Buck Regulators

Bing Yuan; Lang-Qi Xiao; Bing-Yuan Wang; Jing Ying


A 0.007 mm2 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS

Yong-Jun Jo; Ju Eon Kim; Kwang-Hyun Baek; Tony Tae-Hyoung Kim

A 3.36-GHz Locking-Tuned Type-I Sampling PLL With −78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques

Yunbo Huang; Yong Chen; Hailong Jiao; Pui-In Mak; Rui P. Martins


Compact E-Band I/Q Receiver in SiGe BiCMOS for 5G Backhauling Applications

Giandomenico Amendola; Luigi Boccia; Francesco Centurelli; Pascal Chevalier; Alessandro Fonte; Carmine Mustacchio; Andrea Pallotta; Pasquale Tommasino; Antonio Traversa; Alessandro Trifiletti


Adaptive Maximum Power Point Tracking With Model-Based Negative Feedback Control and Improved V–f Model

Yuanfei Wang; Mo Huang; Ping Luo; Yan Lu; Rui P. Martins


A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS

Shiheng Yang; Jun Yin; Tailong Xu; Taimo Yi; Pui-In Mak; Qiang Li; Rui P. Martins


A 38.6-fJ/Conv.-Step Inverter-Based Continuous-Time Bandpass ΔΣ ADC in 28 nm Using Asynchronous SAR Quantizer

Hanie Ghaedrahmati; Jianjun Zhou; Robert Bogdan Staszewski


A −40 °C to 140 °C Picowatt CMOS Voltage Reference With 0.25-V Power Supply

Hongchang Qiao; Chenchang Zhan; Yutian Chen


A 1.3 μW Event-Driven ANN Core for Cardiac Arrhythmia Classification in Wearable Sensors

Qiao Cai; Xinzi Xu; Yang Zhao; Liang Ying; Yongfu Li; Yong Lian


Exploiting Parasitic Capacitances in 3-D Inductors to Design RF CMOS Quasi-Elliptic-Type Broad-Band Bandpass Filters

Xi Zhu; Roberto Gómez-García


A Goertzel Filter-Based System for Fast Simultaneous Multi-Frequency EIS

Louis Regnacq; Yu Wu; Nazanin Neshatvar; Dai Jiang; Andreas Demosthenous


On the Linearity of BJT-Based Current-Mode DAC Drivers

Nicola Lupo; Michele Bartolini; Paolo Pulici; Stefano Colli; Maurizio Nessi; Edoardo Bonizzoni


An FPGA-Based Energy-Efficient Reconfigurable Convolutional Neural Network Accelerator for Object Recognition Applications

Jixuan Li; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui P. Martins


Energy Efficient 0.5V 4.8pJ/SOP 0.93μW Leakage/Core Neuromorphic Processor Design

Vishnu P. Nambiar; Junran Pu; Yun Kwan Lee; Aarthy Mani; Eng Kiat Koh; Ming Ming Wong; Fei Li; Wang Ling Goh; Anh Tuan Do


A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method

Zhiyu Li; Yuhao Huang; Longfeng Tian; Ruimin Zhu; Shanlin Xiao; Zhiyi Yu


HAMBug: A Hybrid CPU-FPGA System to Detect Race Conditions

Danilo Damião Almeida; Lucas Bragança; Frank Sill Torres; Ricardo Ferreira; José Augusto M. Nacif


200-MHz Single-Ended 6T 1-kb SRAM With 0.2313 pJ Energy/Access Using 40-nm CMOS Logic Process

Chua-Chin Wang; Chien-Ping Kuo


An Optimized FPGA-Based Real-Time NDT for 3D-LiDAR Localization in Smart Vehicles

Qi Deng; Hao Sun; Fupeng Chen; Yuhao Shu; Hui Wang; Yajun Ha


Balancing the Cost and Performance Trade-Offs in SNN Processors

Huanliang Zheng; Yuhao Guo; Xingyu Yang; Shanlin Xiao; Zhiyi Yu


A Time-Domain Binary CNN Engine With Error-Detection-Based Resilience in 28nm CMOS

Zhikuang Cai; Boyang Cheng; Yuxuan Du; Xinchao Shang; Weiwei Shan


A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications

Marco Sarmiento; Khai-Duy Nguyen; Ckristian Duran; Trong-Thuc Hoang; Ronaldo Serrano; Van-Phuc Hoang; Xuan-Tu Tran; Koichiro Ishibashi; Cong-Kha Pham