| Year Awarded | Awardee(s) | Paper Title | Publication Title |
| 2022 | Shihui Yin, Zhewei Jiang, Minkyu Kim, Tushar Gupta, Mingoo Seok, Jae-sun Seo | Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 28, Issue 1, January 2020 |
| 2021 | Rana Elnaggar, Krishnendu Chakrabarty, and Mehdi B. Tahoori | Hardware Trojan Detection Using Changepoint-Based Anomaly Detection Techniques | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no 12, Dec. 2019 |
| 2020 | Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flammand, Frank K. Gürkaynak, Luca Benini | Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 10, pp. 2700-2713, Oct. 2017 |
| 2019 | Jason Kamran Eshraghian, Jr., Kyoungrok Cho, Ciyan Zheng, Minho Nam, Herbert Ho-Ching Iu, Wen Lei, Kamran Eshraghian | Neuromorphic Vision Hybrid RRAM-CMOS Architecture | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 12, Dec. 2018 |
| 2018 | Ryan Gary Kim, Wonje Choi, Zhuo Chen, Partha Pratim Pande, Diana Marculescu, and Radu Marculescu | Wireless NoC and Dynamic VFI Co-Design: Energy Efficiency without Performance Penalty | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 7, pp. 2488-2501, July 2016 |
| 2017 | Yingjie Lao and Keshab K. Parhi | Obfuscating DSP Circuits via High-Level Transformations | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 5, May 2015 |
| 2016 | Bayasi, N.; Tekeste, T.; Saleh, H.; Mohammad, B.; Khandoker, A.; Ismail, M. | Low-Power ECG-Based Processor for Predicting Ventricular Arrhthmia | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 5, pp. 1962–1974, May 2016 |
| 2015 | Jaydeep P. Kulkarni, Kaushik Roy | Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 2, pp. 319-332, February 2012 |
| 2014 | Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, and Saibal Mukhopadhyay | A scalable design methodology for energy minimization of STTRAM: A circuit and architecture perspective | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 5, pp. 809-817, May 2011 |
| 2013 | Jing Li, Patrick Ndai, Ashish Goel, Sayeef Salahuddin, Kaushik Roy | Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 12, pp. 1710-1723, December 2010 |
| 2012 | Arkadiy Morgenshtein, Ran Ginosar, Eby G. Friedman, Avinoam Kolodny | Unified Logical Effort—A Method for Delay Evaluation and Minimization in Logic Paths with RC Interconnect | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 5, pp. 689-696, May 2010 |
| 2011 | Eun-Gu Jung, Diana Marculescu, Radu Marculescu, Umit Y. Ogras | Design and Management of Voltage-Frequency Island Partitioned Networks-on-Chip | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 3, pp. 330-341, March 2009 |
| 2010 | Not awarded | ||
| 2009 | Mahalingam Venkataraman, Justin E. Harlow III and Nagarajan Ranganathan | A fuzzy optimization approach for variation aware power minimization during gate sizing | IEEE Transactions on VLSI Systems, vol. 16, no. 8, pp. 975-984, August 2008 |
| 2008 | Not awarded | ||
| 2007 | Zhongfeng Wang, Jun Ma | High-Speed Interpolation Architecture for Soft-Decision Decoding of Reed-Solomon codes | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 9, pp. 937-950, September 2006 |
| 2006 | Bipul C Paul, Animesh Datta, Kaushik Roy, Amit Agarwal, Hamid Mahmoodi | A Process-Tolerant Cache Architecture for Improved Yield in Nanoscale Technologies | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 1, pp. 27-38, January 2005 |
| 2005 | Girish Vishnu Varatkar, Radu Marculescu | On-Chip Traffic Modeling and Synthesis for MPEG-2 Video Applications | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 1, pp. 108-119, January 2004 |
| 2004 | Not awarded | ||
| 2003 | D.E. Duarte, N. Vijaykrishnan, M.J. Irwin | ||
| 2002 | Rafael Maestre, Fadi J. Kurdahi, Milagros Fernandez, Roman Hermida, Nader Bagherzadeh, Hartej Singh | ||
| 2001 | Rajamohana M. Hegde, Naresh R. Shanbhag | ||
| 2000 | Daniel D. Gajski, Jie (Jenny) Gong, Sanjiv Narayan, Frank Vahid | ||
| 1999 | Scott Hauck, Gaetano Borriello, Carl Ebeling | ||
| 1998 | Jean E. Vuillemin, Patrice Bertin, Didier Roncin, Mark Shand, Hervi H. Touati, Philippe Boucard | ||
| 1997 | Teresa Serrano-Gotarredona, Bernabe Linares-Barranco | ||
| 1996 | Chi-Ying Tsui, Jose Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin | ||
| 1995 | Wai-Chi Fang, Chi-Yung Chang, Bing J. Sheu, Oscal Tzyh-Chiang Chen, John C. Curlander |