Year Awarded Awardee(s)Paper Title Publication Title
2019Jason Kamran Eshraghian, Jr., Kyoungrok Cho, Ciyan Zheng, Minho Nam, Herbert Ho-Ching Iu, Wen Lei, Kamran EshraghianNeuromorphic Vision Hybrid RRAM-CMOS Architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Volume: 26, Issue: 12, Dec. 2018)

2018Ryan Gary Kim, Wonje Choi, Zhuo Chen, Partha Pratim Pande, Diana Marculescu, and Radu Marculescu
Wireless NoC and Dynamic VFI Co-Design: Energy Efficiency without Performance Penalty

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 7, pp.  2488-2501, July 2016

2017Yingjie Lao and Keshab K. ParhiObfuscating DSP Circuits via High-Level TransformationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 5, May 2015
2016Bayasi, N.; Tekeste, T.; Saleh, H.; Mohammad, B.; Khandoker, A.; Ismail, M.Low-Power ECG-Based Processor for Predicting Ventricular ArrhthmiaIEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 5, pp. 1962–1974, May 2016
2015Jaydeep P. Kulkarni, Kaushik RoyUltralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 2, pp. 319-332, February 2012
2014Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, and Saibal Mukhopadhyay A scalable design methodology for energy minimization of STTRAM: A circuit and architecture perspective IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 5, pp. 809-817, May 2011
2013Jing Li, Patrick Ndai, Ashish Goel, Sayeef Salahuddin, Kaushik Roy
Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture PerspectiveIEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 12, pp. 1710-1723, December 2010
2012Arkadiy Morgenshtein, Ran Ginosar, Eby G. Friedman, Avinoam KolodnyUnified Logical Effort—A Method for Delay Evaluation and Minimization in Logic Paths with RC InterconnectIEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 5, pp. 689-696, May 2010
2011Eun-Gu Jung, Diana Marculescu, Radu Marculescu, Umit Y. Ogras
Design and Management of Voltage-Frequency Island Partitioned Networks-on-Chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 3, pp. 330-341, March 2009
2010Not awarded
2009Mahalingam Venkataraman, Justin E. Harlow III and Nagarajan Ranganathan
A fuzzy optimization approach for variation aware power minimization during gate sizing
IEEE Transactions on VLSI Systems, vol. 16, no. 8, pp. 975-984, August 2008
2008Not awarded
2007Zhongfeng Wang, Jun MaHigh-Speed Interpolation Architecture for

Soft-Decision Decoding of Reed-Solomon codes

IEEE Transactions on Very Large Scale

Integration (VLSI) Systems, vol. 14, no. 9, pp. 937-950, September 2006

2006Bipul
C Paul, Animesh Datta, Kaushik Roy, Amit Agarwal, Hamid Mahmoodi		A Process-Tolerant Cache Architecture for Improved Yield in Nanoscale TechnologiesIEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 1, pp. 27-38, January 2005
2005Girish
Vishnu Varatkar, Radu Marculescu		On-Chip Traffic Modeling and
Synthesis for MPEG-2 Video Applications		IEEE Transactions on Very Large Scale Integration
(VLSI) Systems, vol. 12, no. 1, pp. 108-119, January 2004
2004Not awarded
2003D.E. Duarte,
N. Vijaykrishnan, M.J. Irwin
2002Rafael
Maestre, Fadi J. Kurdahi, Milagros Fernandez, Roman Hermida, Nader Bagherzadeh,
Hartej Singh
2001Rajamohana
M. Hegde, Naresh R. Shanbhag
2000Daniel
D. Gajski, Jie (Jenny) Gong, Sanjiv Narayan, Frank Vahid
1999Scott
Hauck, Gaetano Borriello, Carl Ebeling
1998Jean E.
Vuillemin, Patrice Bertin, Didier Roncin, Mark Shand, Hervi H. Touati, Philippe
Boucard
1997Teresa
Serrano-Gotarredona, Bernabe Linares-Barranco
1996Chi-Ying
Tsui, Jose Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain,
Bill Lin
1995Wai-Chi
Fang, Chi-Yung Chang, Bing J. Sheu, Oscal Tzyh-Chiang Chen, John C. Curlander