C. M. Lopez et al., "An implantable 455-active-electrode 52-channel CMOS neural probe," 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, CA, 2013, pp. 288-289.

B. C. Johnson et al., "StimDust: A 6.5mm^3, wireless ultrasonic peripheral nerve stimulator with 82% peak chip efficiency," 2018 IEEE Custom Integrated Circuits Conference (CICC), San Diego, CA, 2018, pp. 1-4.

E. Sacco, J. Vergauwen and G. Gielen, "A 16.1-bit Resolution 0.064-mm² Compact Highly Digital Closed-Loop Single-VCO-Based 1-1 Sturdy-MASH Resistance-to-Digital Converter With High Robustness in 180-nm CMOS," in IEEE Journal of Solid-State Circuits.

J. Van Rethy, H. Danneels, V. De Smedt, W. Dehaene and G. E. Gielen, "Supply-Noise-Resilient Design of a BBPLL-Based Force-Balanced Wheatstone Bridge Interface in 130-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 48, no. 11, pp. 2618-2627, Nov. 2013.

J. Marin, E. Sacco, J. Vergauwen and G. Gielen, "A Robust BBPLL-Based 0.18- $\mu$ m CMOS Resistive Sensor Interface With High Drift Resilience Over a −40 °C–175 °C Temperature Range," in IEEE Journal of Solid-State Circuits, vol. 54, no. 7, pp. 1862-1873, July 2019.

F. Tu, S. Yin, P. Ouyang, S. Tang, L. Liu and S. Wei, "Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 8, pp. 2220-2233, Aug. 2017.

J. Jiang, Y. Lu, W. Ki, U. Seng-Pan and R. P. Martins, "20.5 A dual-symmetrical-output switched-capacitor converter with dynamic power cells and minimized cross regulation for application processors in 28nm CMOS," 2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2017, pp. 344-345.

E. Maricau and G. Gielen, "Efficient Variability-Aware NBTI and Hot Carrier Circuit Reliability Analysis," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 12, pp. 1884-1893, Dec. 2010.

E. Maricau and G. Gielen, "Computer-Aided Analog Circuit Design for Reliability in Nanometer CMOS," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 1, no. 1, pp. 50-58, March 2011.

B. Serneels, M. Steyaert and W. Dehaene, "A 237mW aDSL2+ CO Line Driver in Standard 1.2V 0.13μ CMOS," 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, San Francisco, CA, 2007, pp. 524-619.

A. Papanikolaou, H. Wang, M. Miranda and F. Catthoor, "Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design," 13th IEEE International On-Line Testing Symposium (IOLTS 2007), Crete, 2007, pp. 121-121.

B. Dierickx, M. Miranda, P. Dobrovolny, F. Kutscherauer, A. Papanikolaou and P. Marchal, "Propagating variability from technology to system level," 2007 International Workshop on Physics of Semiconductor Devices, Mumbai, 2007, pp. 74-79.

A. Coyette, B. Esen, R. Vanhooren, W. Dobbelaere and G. Gielen, "Automated testing of mixed-signal integrated circuits by topology modification," 2015 IEEE 33rd VLSI Test Symposium (VTS), Napa, CA, 2015, pp. 1-6.

A. Coyette, G. Gielen, R. Vanhooren and W. Dobbelaere, "Optimization of analog fault coverage by exploiting defect-specific masking," 2014 19th IEEE European Test Symposium (ETS), Paderborn, 2014, pp. 1-6.

B. Esen, A. Coyette, N. Xama, W. Dobbelaere, R. Vanhooren and G. Gielen, "A very low cost and highly parallel DfT method for analog and mixed-signal circuits," 2017 22nd IEEE European Test Symposium (ETS), Limassol, 2017, pp. 1-2.

A. Coyette, B. Esen, N. Xama, G. Gielen, W. Dobbelaere and R. Vanhooren, "ADAGE: Automatic DfT-Assisted Generation of Test Stimuli for Mixed- Signal Integrated Circuits," in IEEE Design & Test, vol. 35, no. 3, pp. 24-30, June 2018.

N. Xama, A. Coyette, B. Esen, W. Dobbelaere, R. Vanhooren and G. Gielen, "Automatic testing of analog ICs for latent defects using topology modification," 2017 22nd IEEE European Test Symposium (ETS), Limassol, 2017, pp. 1-6.

G. Gielen et al., "Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 5, pp. 577-586, May 2016.

Marín, Jorge & Van Rethy, Jelle & Vergauwen, Johan & Gielen, Georges, "Digital-domain Chopping Technique for High-Resolution PLL-based Sensor Interfaces", Sensors and Actuators A: Physical, August 2016.

R. Wu, Y. Chae, J. H. Huijsing and K. A. A. Makinwa, "A 20-b ± 40-mV Range Read-Out IC With 50-nV Offset and 0.04% Gain Error for Bridge Transducers," in IEEE Journal of Solid-State Circuits, vol. 47, no. 9, pp. 2152-2163, Sept. 2012.

G. Gielen and E. Maricau, "Stochastic degradation modeling and simulation for analog integrated circuits in nanometer CMOS," 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 2013, pp. 326-331.

G. Gielen, W. Dobbelaere, R. Vanhooren, A. Coyette and B. Esen, "Design and test of analog circuits towards sub-ppm level," 2014 International Test Conference, Seattle, WA, 2014, pp. 1-2.

Z. Jiang, S. Yin, J. Seo and M. Seok, "C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism," in IEEE Journal of Solid-State Circuits.