High-performance embedded memory design in advanced FinFET technologies

Static Random Access Memory (SRAM) technology is the enabler of advanced logic technology node scaling and has significant implications on continuation of Moore’s law. Embedded SRAM capacity is growing across all product segments ranging from battery powered SoCs (IoT edge devices), to high performance ASICs (FPGA, Modems, Microprocessors) to emerging machine learning accelerators (GPU, TPU, NPU). In advanced FinFET technologies, the 2-dimensional scaling is becoming increasingly challenging degrading the SRAM scaling metrics (such as Vmin, bitcell area, array efficiency). This effect is further exacerbated in SRAMs due to the fundamental read vs. write operation conflict as well as worsened interconnect parasitics affecting critical wordline and bitline signal performance.

In this talk, I will describe recent trends in high performance SRAM designs in modern FinFET technologies and discuss various process, device, and circuit innovations enabling continued SRAM scaling. I will also present an overview of other logic technology compatible embedded memories such as ROMs, PROMs, Register files. In addition, various technology scaling boosters such as buried rail technology for sub-5nm FinFETs, 3-D integration (split- 3D, monolithic 3D) will also be presented.