Jaydeep Kulkarni

Jaydeep Kulkarni

Department of Electrical and Computer Engineering University of Texas at Austin
IEEE Region
Region 05 (Southwestern U.S.)

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Jaydeep Kulkarni received a B.E. degree from the University of Pune, India, in 2002, an M. Tech degree from the Indian Institute of Science (IISc) in 2004, and a Ph.D. in Electrical and Computer Engineering from Purdue University in 2009. From 2009-2017, he worked as a Research Scientist at Intel Circuit Research Lab in Hillsboro, OR, and devised energy-efficient circuit technologies for Intel’s next-generation microprocessors. He is an associate professor in the Chandra Department of Electrical and Computer Engineering and a Fellow of Silicon Labs Endowed Chair in Electrical Engineering at the University of Texas at Austin.

Dr. Kulkarni has filed 38 patents, published two book chapters, and more than 120 papers in peer-reviewed journals and conferences. His research focuses on Integrated circuits and systems, specifically ML/AI accelerators, in-memory computing, DTCO/STCO for emerging nano-devices, heterogeneous and 3D integrated circuits, hardware security, and cryogenic computing.

Dr. Kulkarni received the Best M. Tech Student award from IISc Bangalore, Intel Foundation Ph.D. fellowship award, Purdue ECE Outstanding Doctoral Dissertation Award, SRC Inventor Recognition Awards, the IEEE Transactions on VLSI Systems Best Paper Award, the SRC Outstanding Industrial Liaison award, Micron Foundation Faculty Awards, Intel Rising Star Faculty Award, NSF CAREER Award, SRC Innovator Award, UT ECE Junior Faculty Excellence in Teaching Award, and IEEE Best Associate Editor Award.

Dr. Kulkarni has participated in technical program committees of the VLSI Symposium, CICC, ASSCC, DAC, ICCAD, ISLPED, AICAS, and VLSI Design conferences. He has served as a Distinguished Industrial Lecturer for the IEEE Circuits and Systems Society, IEEE Solid-State Circuits Society, and IEEE Electron Device Society. He has been a TPC Co-Chair and General Co-Chair for 2017 and 2018 ISLPED, respectively, and a TPC Co-Chair for the 2023 VLSI Design Conference, India. He has also been an associate editor for IEEE Solid-State Circuit Letters, IEEE, Transactions on VLSI Systems, and IEEE Transactions on Circuits and Systems I and II. He is a senior IEEE and the US National Academy of Inventors member.

Group Website: Circuit Research Lab, http://sites.utexas.edu/CRL/

IEEE CASS Position History:
  • Present   VSA TC Member (VLSI Systems and Applications Technical Committee (VSA TC))
  • 2024-Present   Associate Editor (IEEE Transactions on Circuits and Systems Part I: Regular Papers (TCAS-I) Editorial Board)
  • 2022-Present   Associate Editor TVLSI (IEEE Transactions on Very Large Scale Integration Systems (TVLSI) Editorial Board)
  • 2022-2023   Associate Editor (IEEE Transactions on Circuits and Systems Part II: Express Briefs (TCAS-II) Editorial Board)
  • Recognitions:
  • 2024-2025 Distinguished Lecturer
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