Aryan Kannaujiya is a highly motivated and accomplished professional in VLSI design, currently serving as a Senior Research Fellow at the Indian Institute of Technology (IIT) Jammu. He is pursuing a Ph.D. in VLSI Design with a focus on hardware reliability and security, where he develops CMOS-based circuits that are resilient to soft errors and NBTI degradation. His innovative designs include Schmitt triggers, ring oscillators, SRAM cells, and arrays of SRAM memory.

Achievements and Awards: Winner of the Best Paper Award at the 28th IEEE International Symposium on VLSI Design and Test (VDAT-2024). Secured 1st Rank in the Best Presenter Award and 2nd Rank in the Circuit Design Competition at the Workshop on Robust & Reliable VLSI Circuits, IIT Roorkee.

Grants and Recognition: Awarded an International Travel Grant by the Department of Science and Technology (DST), Government of India, to present his research at the 31st IEEE International Conference on Electronics Circuits and Systems (ICECS-2024).
Received travel support from IIT Jammu to present at the 18th International Conference on Ph.D. Research in Microelectronics and Electronics (PRIME 2024), held in Valencia, Spain.

Aryan has an extensive academic portfolio, with over 24 publications in SCI-indexed journals and international conferences, including contributions to IEEE Transactions on Device and Materials Reliability. With a keen interest in advancing the reliability and robustness of VLSI circuits, Aryan continues to make significant contributions to the field of circuit design and research.