Ayan is a seasoned professional with over 17 years of experience in the VLSI domain. Currently serving as a Technologist at Western Sandisk, he leads the next-gen methodology development team, focusing on advanced digital design methodology for Ultra Deep Submicron nodes.

Prior to his role at Sandisk, Ayan held a prominent position where he led the timing convergence of digital design in High-Performance Intel Cores. During his tenure at Intel, he also spearheaded the development of several PPA (Power, Performance, and Area) design optimization tools, which were successfully implemented across multiple projects.

Ayan's journey in the field of VLSI began at IBM Labs, where he contributed to the design of high-performance processors for eight years. He pursued his M.Tech from Jadavpur University, Kolkata, before joining IBM.

A Senior IEEE member, Ayan has made significant contributions to the academic and research community. He has an impressive publication record with close to 13 papers published in leading IEEE conferences and journals. Additionally, he holds six US patents in his name. Ayan actively participates in various technical review committees for prestigious IEEE conferences such as ISCAS, APCAS, DAC, VLSID, among others. Currently, he is the chair of the IEEE CAS Bangalore Chapter.

Ayan's research interests revolve around methodology development of Digital design, interconnect optimization, power-aware circuit design, and PPA optimization of digital designs. His expertise and passion for innovation continue to drive advancements in the VLSI industry, making him a respected figure in his field.