Fernando Moraes received the Electrical Engineering and M.Sc. degrees from the Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1987 and 1990, respectively. In 1994, he received his Ph.D. from the Laboratoire d'Informatique, Robotique et Microélectronique de Montpellier (LIRMM), France. The thesis (defended in 1994) received the distinction "Très Honorable avec Félicitations du Jury." Another prestigious award is the Best Conceptual Design in the DATE Conference (2005), Europe's premier conference in microelectronics design automation.

He is currently at PUCRS, where he has been an Associate Professor from 1996 to 2002 and a Full Professor since 2002. He joined the Université de Montpellier as an Invited Professor in 1998, 1999, 2000, and 2017 (1 to 3 months each period).

He has authored and co-authored 58 peer-reviewed journal articles on VLSI design, including many-cores, networks-on-chip (NoCs), cryptography, and machine-learning accelerators. One of these articles, HERMES: An Infrastructure for Low Area Overhead Packet-switching Networks on Chip, is cited by more than 800 other papers. He has also authored and co-authored over 280 conference papers on these topics. He has co-advised 4 MSCs, advised 33 MsC, advised 20 PhDs, and co-advised 3 PhD. Mr. Moraes is a member of the program committee of the SBCCI, ISVLSI, NoCs, DATE, and associate editor of IEEE Transactions on Circuits and Systems II: Express Briefs (from 2024). From 2001 to 2006, Mr. Moraes was responsible for the Computer Engineering Course at PUCRS (Brazil). From 2008 to 2010, he was responsible for the Computer Science Graduate Program at PUCRS. His primary research interests include Microelectronics, FPGAs, reconfigurable architectures, security, NoCs, and MPSoCs (multiprocessor system on chip). SBC (Sociedade Brasileira de Computação), SBMICRO, and IEEE Senior Member.