Takayuki Kawahara

Tokyo University of Science
IEEE Region
Region 10 (Asia and Pacific)

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Takayuki Kawahara (M’91-SM’98-F’07) received B.S. and M.S. degrees in physics and a Ph.D. in electronics from Kyushu University, Fukuoka, Japan in 1983, 1985, and 1993.

In 1985, he joined the Central Research Laboratory (CRL), Hitachi Ltd., where he made fundamental contributions in many areas in the field of low-power memories. In the field of DRAM circuits, his major contributions related to low-voltage circuits, including subthreshold-current reduction by gate-source self-reverse biasing in 1993 and an over-drive sense-amplifier scheme coupled with direct sensing. He also pioneered the charge-recycling scheme, reported in 1993, which is now widely applied in various circuits. In the field of flash memory, he and his team developed a 128-Mb chip in 1996 with a bit-line clamped sensing scheme for fast sensing and a high-voltage generator scheme under a low-voltage supply. In addition, he led the ultra-low-power System LSI Project at CRL. In the field of emerging memory and devices, he reported the world’s first fully functional 2-Mb STT-RAM proto chip in 2007, and his team developed FD-SOI SRAM circuitry with back-gate control. After that, he was engaged in the development of circuitry for DNA sequencers (statistical nano-pore and fast ISFET arrays).

In 2014, he became a professor in the Department of Electrical Engineering at the Tokyo University of Science, Tokyo, Japan. Sustainable electronics is the focus of his lab, which includes low-power artificial intelligence (AI) devices and circuits, sensors and AI signal processing, spin current applications and quantum computing techniques. In particular, the achievements of the fully-coupled Ising machine LSI have been highly regarded.

From 1997 to 1998, he was a visiting researcher at the Electronics Laboratory (LEG) in the Swiss Federal Institute of Technology, Lausanne, Switzerland (EPFL). He was the secretary/publicity officer of the 2006/2007 JFE Committee of Symposium on VLSI Circuits, an IEEE SSCS distinguished lecturer in 2008/2009, and the FE regional chair of IEEE ISSCC 2009/2010. He is a recipient of the 9th (2009) Yamazaki-Teiichi Prize, a 2014 IEICE Electronics Society Award, and the Prize for Science and Technology (Development Category) at the FY2017 Commendation for Science and Technology by the Minister of Education, Culture, Sports, Science and Technology of Japan. He is an IEEE Fellow.

IEEE CASS Position History:
  • 2022-2023   Associate Editor (IEEE Transactions on Circuits and Systems Part I: Regular Papers (TCAS-I) Editorial Board)
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