2015 Synopsys Digital Track Training

This 3-day workshop covers the back- and front-end design flow for digital integrated circuits with Synopsys tools. The course is imparted by Synopsys engineers and it includes lectures with quizzes to test for understanding, as well as challenging labs.
Topics:
Introduction to digital world and ASIC design flow
Fundamentals of digital design
The digital design flow
Test benches and verification
Synopsys tools Design Compiler, IC Compiler, VCS
Design project
Instructors: Victor Grimblatt, Gonzalo A. Fernández, Juan Pablo Moreno, Synopsys, R&D Center Chile.
Investment: $200, IEEE-Members $130, IEEE-CASS $100, Students $70, IEEE Students $50.
For the full program and more information please visit: www.sites.ieee.org/costarica-cas/synopsyscourse2015
Space is limited. To reserve your seat, please RSVP to (Click to show email),https://meetings.vtools.ieee.org/m/35449