2015 Workshop: Using Analog Design to Make Digital Better: Efficient RISC-V Processor in 28nm FDSOI

This talk presents a design of an energy-efficient microprocessor that implements several techniques for operation in a very wide voltage range. A particular implementation is based on an open Berkeley RISC-V architecture. To enable agile dynamic voltage and frequency scaling, with high energy efficiency the design implements an integrated switched-capacitor DC-DC converter. A custom-designed SRAM-based cache operates in a wide 0.45-1V supply range. Techniques that enable low-voltage SRAM operation include 8T cells, assist techniques and differential read. Architectural resiliency techniques include the use of error correction and dynamic column redundancy. The processor is implemented by using an agile design methodology.