Paper

A 0.36 pJ/bit, 0.025 mm2, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology

Volume Number:
63
Issue Number:
9
Pages:
1393
–
1403
Publication Date:
August 2016

paper Menu

Abstract

This paper describes a power and area-efficient forwarded-clock (FC) receiver and includes an analysis of the jitter tolerance of the FC receiver. In the proposed design, jitter tolerance is maximized according to the analysis by employing a delay-locked loop (DLL) based de-skewing. A sample-swapping bang-bang phase-detector (SS-BBPD) eliminates the stuck locking caused by the finite delay range of the voltage-controlled delay line (VCDL), and also reduces the required delay range of the VCDL by half. The proposed FC receiver is fabricated in 65-nm CMOS technology and occupies an active area of 0.025 mm 2 . At a data rate of 12.5 Gb/s, the proposed FC receiver exhibits an energy efficiency of 0.36 pJ/bit, and tolerates 1.4-UI pp sinusoidal jitter of 300 MHz.

Description

W. Bae, G. Jeong, K. Park, S. Cho, Y. Kim and D. Jeong, "A 0.36 pJ/bit, 0.025 mm${}^{\text{2}}$, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 9, pp. 1393-1403, Sept. 2016, doi: 10.1109/TCSI.2016.2578960.