A 40-Gb/s transimpedance amplifier (TIA) is proposed using multistage inductive-series peaking for low group-delay variation. A transimpedance limit for multistage TIAs is derived, and a bandwidth-enhancement technique using inductive-series π -networks is analyzed. A design method for low group delay constrained to 3-dB bandwidth enhancement is suggested. The TIA is implemented in a 0.13-μm CMOS process and achieves a 3-dB bandwidth of 29 GHz. The transimpedance gain is 50 dB·Ω , and the transimpedance group-delay variation is less than 16 ps over the 3-dB bandwidth. The chip occupies an area of 0.4 mm 2 , including the pads, and consumes 45.7 mW from a 1.5-V supply. The measured TIA demonstrates a transimpedance figure of merit of 200.7 Ω/pJ.
J. Kim and J. F. Buckwalter, "Bandwidth Enhancement With Low Group-Delay Variation for a 40-Gb/s Transimpedance Amplifier," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 8, pp. 1964-1972, Aug. 2010, doi: 10.1109/TCSI.2010.2041502.