In the last few years, several digital implementations of phase-locked loops (PLLs) have emerged, in some cases outperforming analog ones. Some of these PLLs use a bang-bang phase detector to convert the phase error into a digital value. Unfortunately, that introduces a hard nonlinearity in the loop which prevents the use of the traditional linear analysis. Nevertheless, authors resort to linearized models for the noise analysis of this kind of loops, but to the author's knowledge, no attempt has been made to evaluate the limits of this approach. In this paper, we address the problem of investigating the limits of the linearized approach, and we apply it to the computation of the jitter transfer and the jitter generation depending on the level of noise at the binary phase detector input. The results will be compared to phase noise measurements obtained from a digital bang-bang PLL implemented in 130-nm CMOS technology.
N. Da Dalt, "Linearized Analysis of a Digital Bang-Bang PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 11, pp. 3663-3675, Dec. 2008, doi: 10.1109/TCSI.2008.925948.