A scalable design methodology for energy minimization of STTRAM: A circuit and architecture perspective

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A scalable design methodology for energy minimization of STTRAM: A circuit and architecture perspective

Volume Number:

Issue Number:

Pages:

809

–

817

Publication Date:

25 February 2010

Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay

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Abstract

In this paper, we analyze the energy dissipation in spin-torque-transfer random access memory array (STTRAM). We present a methodology for exploring the design space to minimize the energy dissipation of the array while maintaining required read and write quality for a given magnetic tunnel junction technology. The proposed method shows the need for proper choice of the silicon transistor width and array operating voltage to minimize the energy dissipation of the STTRAM array. The write energy is found to be 10 × greater than read energy. Hence, read-write ratio becomes a crucial factor that determines energy for STTRAM last level caches (L2). An exploration is performed across several architectural benchmarks including shared and non-shared caches for detailed energy analysis.

Description

S. Chatterjee, M. Rasquinha, S. Yalamanchili and S. Mukhopadhyay, "A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 5, pp. 809-817, May 2011, doi: 10.1109/TVLSI.2010.2041476.