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Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories

Issue Number:
2
Volume Number:
61
Pages:
Starting page
443
Ending page
454
Author(s)
Weisheng Zhao; Mathieu Moreau; Erya Deng; Yue Zhang; Jean-Michel Portal; Jacques-Olivier Klein; Marc Bocquet; Hassen Aziza; Damien Deleruyelle; Christophe Muller; Damien Querlioz; Nesrine Ben Romdhane; Dafiné Ravelosona; Claude Chappert

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Abstract

Emerging non-volatile memories (NVM) based on resistive switching mechanism (RS) such as STT-MRAM, OxRRAM and CBRAM etc., are under intense R&D investigation by both academics and industries. They provide high write/read speed, low power and good endurance (e.g., > 10 12 ) beyond mainstream NVMs, which allow them to be embedded directly with logic units for computing purpose. This integration could increase significantly the power/die area efficiency, and then overcome definitively the power/speed bottlenecks of modern VLSIs. This paper presents firstly a theoretical investigation of synchronous NV logic gates based on RS memories (RS-NVL). Special design techniques and strategies are proposed to optimize the structure according to different resistive characteristics of NVMs. To validate this study, we simulated a non-volatile full-adder (NVFA) with two types of NVMs: STT-MRAM and OxRRAM by using CMOS 40 nm design kit and compact models, which includes related physics and experimental parameters. They show interesting power, speed and area gain compared with synchronized CMOS FA while keeping good reliability.

Description

IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 2, pp. 443-454, Feb. 2014, doi: 10.1109/TCSI.2013.2278332.