Device Aware Test: The Means to Win the War Against Unmodeled Faults

Testing defects in logic and memory chips underwent a long evolution process. Testing went from early functional test methods to structural testing driven by well-defined fault models. The development of such models assumes that physical defects in devices can be modeled as linear resistors. Although it can be convincing for modeling opens and shorts in interconnects, this assumption has never been validated for devices. In addition, it is well known that scaling below 10nm is giving rise to many device failure mechanisms that cannot be modeled by linear resistors; not to mention emerging devices which are by nature non-linear such as RRAMs, PCMs and STTMRAMs. This tutorial introduces Device-Aware Test (DAT) as a mean to close the gap between manufacturing defects and the way they can be modeled. DAT does not assume that a defect in a device (or a cell) can be modeled electrically as a linear resistor (as the state-of-the art approach 2021-2022 CASS Distinguished Lecturer Roster suggests), but it rather incorporates the impact of the physical defect in the technology parameters of the device and thereafter in its electrical parameters. Once the defective electrical model is defined, a systematic fault analysis is performed to derive appropriate fault models and subsequently test solutions. The tutorial demonstrates the application/use and the superiority of DAT approach based on two industrial memory designs: STT-MRAMs and RRAMs. For the considered memories, the industrial results will be presented to show that DAT sensitizes realistic faults as well as new unique defects and faults that can never be caught with the traditional approach. In addition, the results will show how powerful is DAT for fast diagnosis and yield learning.