CASS-Wide Webinar Talk I: "Graphene-Based Computing"

In this presentation, we argue and provide Non-Equilibrium Green’s Function Landauer formalism-based simulation evidence that in spite of Graphene’s bandgap absence, Graphene Nanoribbons (GNRs) can provide support for energy-effective computing.  We start by demonstrating that: (i) band gap can be opened by means of GNR topology and (ii) GNR’s conductance can be molded according to some desired functionality, i.e., 2- and 3-input AND, NAND, OR, NOR, XOR, and XNOR, via shape and electrostatic interaction. Afterward, we introduce a generic GNR-based Boolean gate structure composed of a pull-up GNR performing the gate Boolean function and a pull-down GNR performing the gate inverted Boolean function, and, by properly adjusting GNRs' dimensions and topology, we design and evaluate by means of SPICE simulations inverter, buffer, and 2-input GNR based AND, NAND, and XOR gates. Compared with state-of-the-art graphene FET and CMOS-based counterparts the GNR-based gates outperform its challengers, e.g., up to 6x smaller propagation delay, 2 orders of magnitude smaller power consumption while requiring 1 to 2 orders of magnitude smaller active area footprint than 7nm CMOS equivalents. Finally, to get a better inside into the practical implications of the proposed approach, we present Full Adder (FA) and SRAM cell GNR designs, as they are currently fundamental components for the construction of any computation system. For an effective FA implementation, we introduce a 3-input MAJORITY gate, which apart of being able to directly compute FA's carry-out is an essential element in the implementation of Error Correcting Codes codecs, that outperforms a 7nm CMOS equivalent Carry-Out calculation circuit by 2 and 3 orders of magnitude in terms of delay and power consumption, respectively, while requiring 2 orders of magnitude less area. The proposed FA exhibits 6x smaller delay, 3 orders of magnitude less power consumption while requiring 2 orders of magnitude less area than a 7 nm FinFET CMOS counterpart. However, because of the effective carry-out circuitry, a GNR-based n-bit Ripple Carry Adder, whose performance is linear in the Carry-Out path delay, will be 108x faster than an equivalent CMOS implementation. The GNR-based SRAM cell provides a slightly better resilience to DC-noise characteristics, while performance-wise has a 3x smaller delay, consumes 2 orders of magnitude less power, and requires 1 order of magnitude less area than the CMOS equivalent. These results clearly indicate that the proposed GNR-based approach is opening a promising avenue toward future competitive carbon-based nanoelectronics. 

Bio
Currently, I am an Associate Professor with the Computer Engineering Laboratory, Electrical Engineering, Mathematics and Computer Science Faculty, Delft University of Technology, Delft, The Netherlands. I received the MSc degree in Computer Science from "Politehnica" University of Bucharest, Bucharest, Romania, and the PhD degree in Electrical Engineering from Delft University of Technology, The Netherlands.

I am an IEEE Fellow and a HiPEAC member.

My current research is focused on: (i) unconventional computation paradigms and computation with emerging nano-devices, (ii) the design and implementation of dependable/reliable systems out of unpredictable/unreliable components, and (iii) ageing assessment/prediction and lifetime reliability aware resource management.

I (co-)authored more than 250 papers in peer-reviewed international journals and conferences, received 12 Best Paper Awards in international conferences, e.g., 2016 IEEE/ACM International Symposium on Nanoscale Architectures, 2012 IEEE Conference on Nanotechnology, 2012 ACM/IEEE International Symposium on Nanoscale Architectures, 2005 IEEE Conference on Nanotechnology, and 2001 International Conference on Computer Design.

In the last decade, I have been involved in European Union funded research projects, e.g., i-RISC, 3DIM3, NEMSIC, as Principal Investigator and Work Package Leader.

I served as Associate Editor for IEEE Transactions on CAS I (2009-2011), IEEE Transactions on Nanotechnology (2008-2014), Microprocessors and Microsystems (2016-2017), and Nano Communication Networks (2010-2014);  Associate Editor in Chief for IEEE Transactions on Nanotechnology (2015 - 2019); Senior Editorial Board Member for IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2016-2017); Steering Committee Member for IEEE Transactions on Multi-Scale Computing Systems (2014-2018); Chair of the Giga-Nano IEEE CASS Technical Committee (2013-2015); and IEEE Nanotechnology Council CASS representative (2013-2014).

I have been actively involved in the organization of numerous international conferences as General Chair (e.g., NANOARCH 2018), Technical Program Committee (TPC) Chair (e.g., NANOARCH 2012), Track Chair, (e.g., ISCAS 2014-2016), Special Sessions Chair, (e.g., ICECS 2016), Workshop Chair, (e.g., ESSCIRC 2013), and TPC Member (e.g., ISCAS, DATE, ARITH, NANOARCH, GLSVLSI).

Currently, I am Editor in Chief for IEEE Transactions on Nanotechnology, Associate Editor for IEEE Transactions on Computers, CASS BoG member (2020-2022), and CASS Distinguished Lecturer (2019-2020).

Presently, I am co-Principal Investigator of the EU FET Open “Spin Wave Computing for Ultimately-Scaled Hybrid Low-Power Electronics” (CHIRON) project and my teaching includes MSc Computer Engineering courses Modern Computer Architecture (ET4074), Computer Arithmetic (ET4170), and Processor Design (ET4171).