2022 IEEE CASS Industry Forum on Challenges in Formal Verification of ASIC Chips

The goal of this project is to ensure participants use and understand a formal verification tool that checks all functionality of the RTL and GTL code to prove they are equivalent to one another. This program covers 100% of all the functions inside the code which is known as formal equivalence check. The Mentor FormalPro tool allows for easy debugging with the use of a built in GUI and several types of reports that provide information on errors within the code. This program will also help the participants to analyse anf design to achieve minimum energy operation for the targeted performance in a wide range of frequencies.

Scope: The result of this program will help our participants in understanding the verification of the three main blocks of code that make
up the chip. The last step to be completed was the verification of all the blocks together to ensure the chip functioned in equivalent. Thus, on the one day of the program we are planning to share knowledge and obtain in working with this new tool to a co-worker. This was done so that the tool will be better understood as I devoted all time working with the tool versus someone trying to figure out the tool on top of doing other important work. Overall this program helps the researchers in understanding PLSense to ramp-up their equivalence check process in the fastest manner possible while using it to verify their newest chip.

Table of Contents (Tentative)

1. Signing off ASIC Chips- An Overview
2. Formal verification for faster SoC tapeouts
3. Design methodologies for meeting aggressive PPA targets

Venue: T-Hub, Gachibowli Hyderabad, India. 501218