RISC V and VLSI Chip Design Roadshow

Report: RISC-V and VLSI Chip Design Roadshow

Introduction:
On April 12th, 2024, the RISC-V and VLSI Chip Design Roadshow Workshop took place at the Cambridge Institute of Technology. This event aimed to bridge the gap between theoretical knowledge and practical skills in the field of Very Large Scale Integration (VLSI) design using the RISC-V architecture.

Key Highlights:
1. Hands-On Experience:
• The workshop was highly interactive, featuring lab exercises with RISC-V GCC, Verilog RTL simulation, and synthesis using Electronic Design Automation (EDA) tools.
• Participants gained practical insights into physical design verification, GDS (Graphic Data System) generation, and direct programming of RISC-V boards.
2. Industry Collaboration:
• The event attracted students, researchers, and faculty members.
• Partnerships with leading companies such as Synopsys, Thales India, and SAMSUNG facilitated knowledge exchange and real-world exposure.
3. Learning Opportunities
• Participants explored computer architecture, chip design, and embedded systems
• The workshop covered topics related to RISC-V, VLSI, open-source EDA tools, and microcontroller programming.
4. Impact and Future Prospects
• The workshop empowered attendees with practical skills, preparing them for careers in VLSI design.
• It fostered a community of skilled professionals passionate about shaping the future of technology.

Conclusion:
The RISC-V and VLSI Chip Design Workshop at Cambridge Institute of Technology was a resounding success, emphasizing the importance of hands-on learning and industry collaboration. As we move toward an era of innovation, events like these play a crucial role in unlocking the potential of India’s semiconductor landscape.