TVLSI Current Issue

Aims & Scope
IEEE Transactions on Very Large Scale Integration (VLSI) Systems covers design and realization of microelectronic systems using VLSI/ULSI technologies that require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.

To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded. The editorial board, consisting of international experts, invites original papers which emphasize the novel system integration aspects of microelectronic systems, including interactions among system design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and system level qualification. Thus, the coverage of this Transactions focuses on VLSI/ULSI microelectronic system integration.

Topics of special interest include, but are not strictly limited to, the following: • System Specification, Design and Partitioning, • System-level Test, • Reliable VLSI/ULSI Systems, • High Performance Computing and Communication Systems, • Wafer Scale Integration and Multichip Modules (MCMs), • High-Speed Interconnects in Microelectronic Systems, • VLSI/ULSI Neural Networks and Their Applications, • Adaptive Computing Systems with FPGA components, • Mixed Analog/Digital Systems, • Cost, Performance Tradeoffs of VLSI/ULSI Systems, • Adaptive Computing Using Reconfigurable Components (FPGAs) 

TVLSI Current Issue

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - new TOC

January 2025

Table of Contents

Volume: 33 Issue: 1 | Date of Publication: 30 December 2024

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information

Volume: 33 Issue: 1 | Date of Publication: 30 December 2024

A Fast Design Optimization of On-Chip Equalizing Links Using Particle Swarm Optimization

Hyoseok Song; Kwangmin Kim; Gain Kim; et al.
Volume: 33 Issue: 1 | Date of Publication: 5 December 2024

A 16-bit 1-MS/s SAR ADC With Capacitor Mismatch Self-Calibration

Jie Ding; Fuming Liu; Kuan Deng; et al.
Volume: 33 Issue: 1 | Date of Publication: 14 November 2024

CR-DRAM: Improving DRAM Refresh Energy Efficiency With Inter-Subarray Charge Recycling

Haitao Du; Hairui Zhu; Song Chen; et al.
Volume: 33 Issue: 1 | Date of Publication: 11 September 2024

A 0.05–1.5-GHz PVT-Insensitive Digital-to-Time Converter for QKD Applications

Haiyue Yan; Yan Ye; Wenjia Li; et al.
Volume: 33 Issue: 1 | Date of Publication: 30 August 2024

A Single-Stage Gain-Boosted Cascode Amplifier With Three-Layer Cascode Feedback Amplifier for Front-End SHA in High-Linearity Pipelined ADC

Yu Liu; Yupeng Shen; Mingliang Chen; et al.
Volume: 33 Issue: 1 | Date of Publication: 19 August 2024

A Hybrid Domain and Pipelined Analog Computing Chain for MVM Computation

Tianzhu Xiong; Yuyang Ye; Xin Si; et al.
Volume: 33 Issue: 1 | Date of Publication: 26 September 2024

Detect and Replace: Efficient Soft Error Protection of FPGA-Based CNN Accelerators

Zhen Gao; Yanmao Qi; Jinchang Shi; et al.
Volume: 33 Issue: 1 | Date of Publication: 26 August 2024

MCM-SR: Multiple Constant Multiplication-Based CNN Streaming Hardware Architecture for Super-Resolution

Seung-Hwan Bae; Hyuk-Jae Lee; Hyun Kim
Volume: 33 Issue: 1 | Date of Publication: 4 December 2024

TVLSI Popular Articles

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Popular

November 2024

Physical Attack Protection Techniques for IC Chip Level Hardware Security

Makoto Nagata; Takuji Miki; Noriyuki Miura
Volume: 30 Issue: 1 | Date of Publication: 5 May 2021

Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator

Samaneh Babayan-Mashhadi; Reza Lotfi
Volume: 22 Issue: 2 | Date of Publication: 11 February 2013

Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process

Eunbin Park; Taigon Song
Volume: 31 Issue: 2 | Date of Publication: 21 November 2022

FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Networks With Efficient DSP and Memory Optimization

Jindong Li; Guobin Shen; Dongcheng Zhao; et al.
Volume: 31 Issue: 8 | Date of Publication: 5 June 2023

A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection

Duy Thanh Nguyen; Tuan Nghia Nguyen; Hyun Kim; et al.
Volume: 27 Issue: 8 | Date of Publication: 31 March 2019