CASS-Wide Webinar XXV: Signal and Power Integrity Challenges in Advanced Packaging Technologies for Disaggregated Integration

The integrated circuit industry faces new challenges as chip complexity and area have been increasing to prohibitive ranges. Some segments have been adopting then a relatively new paradigm for heterogeneous integration based on chiplets at the first package level in combination with advanced 2.5 and 3D packaging technologies. 

The chiplet approach has the advantage of reducing the single die complexity and size, which is compatible with a high silicon yield, but also allows a faster evolution of electronics systems by a selective redesign of certain chips within a disaggregated solution, or the customization of the system by certain chiplet combinations. Nevertheless, this dense packaging integration imposes signal and power integrity challenges, as well as the necessity of new circuitry and novel validation and test methodologies to handle parallel-massive communication across dies. 

This lecture discusses the challenges associated with advanced packaging technologies and chiplet integration from the electrical integrity perspective, where high-density and high-speed signaling, and narrow areas for power distribution impose some interesting trade-offs among performance and reliability, together with the need of a new kind of interface, called the embedded IO (EIO), for chip-to-chip communication.