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- A 0.61-μJ/Frame Pipelined Wired-logic DNN Processor in 16-nm FPGA Using Convolutional Non-Linear Neural Network
- Stability Boundaries of Wide-Input-Range COT Buck Converters With Ripple Compensation
- A Natively Fixed-Point Run-Time Reconfigurable FIR Filter Design Method for FPGA Hardware
- Optimization of Quantized Analog Signal Processing Using Genetic Algorithms and μ-Law
- Self-Repairing Carry-Lookahead Adder With Hot-Standby Topology Using Fault-Localization and Partial Reconfiguration
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