Special Issue on 2.5-D/3-D Chiplet Circuits and Systems, EDA, Advanced Packaging, and Test—Part II

Dear IEEE JETCAS Readers, 

The IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) proudly published its December 2025 issue that presents the latest technological breakthroughs and research advancements in chiplet circuits. Following Part I of the Special Issue, Part II continues the deep exploration of chiplet technology by addressing the remaining critical topics: system-on-chip (SoC) architecture, chiplet interconnect, and electronic design automation (EDA) tools in 12 papers. While Part I focused on the physical realization of chiplet SoC systems through advanced packaging innovations and rigorous testing methodologies, Part II shifts the emphasis toward design-level challenges that will impact chiplet-based SoC system’s performance and implementation efficiency. It presents resolutions to architecture design challenges such as deadlock in network on chip (NoC), discusses ways to improve energy and design efficiency in 2.5-D and 3-D IC, explores how interconnect protocols’ performance will be improved and support specific chiplet applications, and investigates different EDA tools to facilitate design space exploration and to implement multiphysics cooptimization. Together, these two parts provide a complete view of the chiplet technology landscape, addressing both the enabling physical technologies and the design methodologies required to fully realize the transformative potential of chipletbased SoC systems.

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Best Regards, 

Chi-Tsun (Ben) Cheng (Editor-in-Chief) 

Erivelton Nepomuceno (Associate Editor-in-Chief) 

Manisha Guduri (Associate Editor-in-Chief for Digital Communications)