Special Issue on 2.5D/3D Chiplet Circuits and Systems, EDA, Advanced Packaging, and Test — Part I

Special Issue on 2.5D/3D Chiplet Circuits and Systems, EDA, Advanced Packaging, and Test — Part I
JETCAS Volume 15, Issue 3, September 2025

Dear IEEE JETCAS Readers, 

The IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) proudly published its September 2025 issue that presents the latest technological breakthroughs and research advancements in chiplet technology. The collected contributions from leading researchers and industry practitioners address topics including innovative accelerator chiplet and Network-on-Chip (NoC) design, advanced interconnect protocols and physical performance improvement, specific EDA tools such as design space exploration (DSE) and multi-physics co-optimization, breakthrough packaging technologies and thermal management approaches, and comprehensive testing and Design-for-Test (DfT) strategies that ensure the performance, cost-effectivity, and reliability of chiplet-based technologies and products across diverse application domains. This is the first part of a double issue and comprises 12 papers covering two main topics of chiplet-based systems: advanced packaging and test.

Remember that you can find the latest news of JETCAS in our LinkedIn page.

Best Regards,
Wen-Hsiao Peng (Editor-in-Chief)
Shimeng Yu (Associate Editor-in-Chief)
Sergi Abadal (Associate Editor-in-Chief for Digital Communications)