2.5D/3D Vertical Power Delivery for Chiplet Systems

With the surging demands for extremely high current at sub-1V supply voltage level in high performance computing and AI training centers, conventional planar power delivery architecture on the XPU cards suffers from high I2R loss in the “last-millimeter” power delivery. With 48V replacing 12V bus, efficient high-density power conversion becomes one of the main bottlenecks for system integration. There is a wide voltage gap between the power bus and the digital rails at the point-of-load (PoL), calling for novel power conversion topologies and system architectures. To bridge this gap, switched-capacitor-inductor (SCI) hybrid DC-DC converter has been one of the hottest topics in the power management IC area. Meanwhile, recent advanced 2.5D/3D packaging technologies enable more design flexibility and topology innovations for the PoL vertical power delivery, especially in chiplet systems. In this talk, we will analyze the difficulties and introduce a few hybrid SCI DC-DC design examples from our research group. Then, we will share several of our observations and design suggestions for future works.