Channel equalization and signal integrity in memory interfaces


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While DRAM bandwidth continues to scale at an exponential pace, a trend that will only intensify through the proliferation of AI-driven applications, the intrinsic signal integrity of the memory subsystem has not kept up. Degradation in signaling margin stems from both the pressure to suppress board, package and integration manufacturing costs and the pressure to retain specific system-level architectural embodiments, including multi-rank and multi-module memory channel configurations. To address the growing challenges in DRAM communications, every branch of the Double-Data-Rate (DDR) family has adopted, or is in the process of adopting, one or more forms of channel equalization. This presentation will discuss the growing signaling challenges associated with the most common DRAM subsystems and how those are currently addressed at the interface level. It will further project future requirements as the demand for DRAM bandwidth continues to scale without signs of slowing. 

This presentation will be tutorial in nature, covering both the basics of channel equalization theory and implementation in the context of memory, as well as some basic points of signal integrity as it relates to the design and manufacturing of chip-to-chip interconnects.