Cryogenic Circuits and Systems for Next Generation AI Cold Computing

Generative AI is creating unprecedented demands for performance enhancement. Cryogenic CMOS has emerged as a compelling solution leveraging improved subthreshold slope (SS) to achieve performance gains. This work demonstrates that unlocking these benefits requires strategic material optimizations to exploit the full potential of cryogenic. Specifically, we show that optimizing transistor work functions is vital for translating SS improvements into the required increase in ON current, and optimizing interconnect materials to exhibit superconductivity at cryogenic is crucial for eliminating resistive parasitics. Our 2 nm GAA RTL-to-GDS analysis investigates a 64-bit RISC-V processor and AI accelerator. It demonstrates that our material optimizations provide a 3× increase in TOPS, 7.7× increase in TOPS/W, and 23× improvement in efficiency (TOPS2 /W).