Cryogenic CMOS Circuit Design for Superconducting Qubit Interfacing in Quantum Computing Systems

Quantum computing (QC) has increasingly drawn attention in recent years for its potential power and efficiency in a wide range of possible applications. The most important requirement in developing QC techniques is to scale the QC system, i.e., to increase the number of qubits while reducing the system size. There are two main challenges in further scaling the QC system. Firstly, the qubit number is limited by the cooling power of the dilution refrigerator. Secondly, a huge number of cables are required to connect the qubits to the control electronics at room temperature (RT). One potential approach to overcome these challenges is to replace the control electronics operating at RT with cryogenic CMOS (cryo-CMOS) circuits at 3-4 K. Recent works have focused on reducing the power consumption of cryo-CMOS circuits. In this talk, the design considerations, circuit details and measurement results of a cryogenic CMOS interfacing chipset which can be used to control and readout the states of transmon qubits will be covered. To reduce the power consumption of this interfacing chipset such that to increase the number of qubits that can be integrated in a quantum computing system, a controlling pulse generator and a phase-domain qubit state readout circuit both based on the polar architecture are proposed. The circuit architecture as well as the transistor level design techniques will be given. The measurement results of the presented chipset in 3.5-4K temperature when interfacing with the superconducting qubits in 10mK environment will be presented. The possible solutions for the future scalable quantum computing system will also be briefly discussed in this talk.