Development of the first M-PAM-enabled memory interface


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Demands for DRAM bandwidth have far outpaced DRAM transistor performance. Given the costly alternatives of major process technology investments to scale beyond the sixth generation of Graphics DDR (GDDR) or replacing GDDR6 in system architectures with much more expensive high bandwidth memory (HBM), the memory industry has recently stepped into the multi-level signaling domain in order to simultaneously boost pin- and energy-efficiency. GDDR6x, the industry’s first PAM-4-enabled, single-ended DRAM interface, successfully demonstrated the viability and benefits of multi-level GPU-to-DRAM communication through enabling the highest speed graphics cards available since its introduction in the Fall of 2020. In doing so, GDDR6x paved the way for the recently released GDDR7 JEDEC standard, which will rely on PAM-3 to achieve its lifetime performance targets in the coming years.

This presentation will share the motivations and considerations that went into the GDDR6x interface, and will describe how building upon the existing GDDR6 architecture, evolutionary modifications to the transceiver, clocking, and data path, along with the component package design, have improved energy-efficiency while enabling data rates from 19 – 24 Gb/s/pin in high volume production. The talk will conclude with a look into the future, including anticipated bottlenecks in continued DRAM bandwidth scaling along with potential solutions, including insights into the recently released GDDR7 standard.