Embedded SRAM Design Challenges on the Cutting-Edge Logic Technologies

In high-performance computing (HPC) applications, embedded memories play an important role. Typically, high-density (HD), high-current (HC), or low-voltage (LV) single-port (SP) 6T-static random-access memory (SRAM) are used for middle-/last-level cache in advanced FinFET technologies because of their logic friendly bitcells without any memory-specific devices such as MRAM or RRAM. Since HPC systems strive for improved power efficiency along with their required computing workload, a wide voltage range operation is essential for enhanced dynamic voltage-frequency scaling (DVFS). To meet such requirements, we implement a cache memory based on HC 6T-SRAM bitcell, which enables high-speed operation at overdrive high-voltage and green power operation at ultralow-voltage. Another approach to enhance power efficiency is the dual power rail design. Although dual-rail SRAM is an effective solution to meet the increasing demands for low-power applications, the performance degradation at low voltage presents a challenge to achieve the high-performance cache target in recent computing systems. The requirement of many level shifters for the design of dual-rail SRAM is another disadvantage as it reduces energy savings and increase area overhead.

In the first part of this talk, a 3-nm FinFET SRAM design is introduced. The row decoder leakage saving (RDLS) and high-speed write driver leakage saving (HS-WDLS) circuits are proposed to reduce leakage power while keeping high access speed. The proposed circuits achieve a 71% reduction in leakage power. The overhead of switching power is 0.3% and 1.9% for read and write operations, respectively. Silicon measurements demonstrate that it operates at a frequency of 3.7 GHz at 1.4 V and has a wide-range operation down to 0.5 V. It achieves the best figure of merit (FoM), defined as density ×Fmax.

In the second part of this talk, another 3-nm FinFET SRAM macro is proposed that utilizes a far-end pre-charge (FPC) circuit and weak-bit (WB) tracking circuit. These circuits can decrease write cycle time by decreasing the pre-charge period and engaging read cycle time by enhancing the trackability of sense enable timing over supply voltage. The bit density is 27.6 Mbit/mm2 and it achieved an operation of 1.9 GHz at 0.75 V and 85 °C, which is 35% faster than conventional performance. Measured silicon data demonstrate a wide operating voltage range of 0.48–1.2 V. This proposal has also achieved the best figure of merit (FoM) compared to other works, as defined by density × access per second (APS)/supply voltage (VDD).

In the last part of this talk, a double-pumped 1-read and 1-write pseudo-2-port 6T SRAM are introduced. The folded bitline (BL) multi-bank (MB) architecture is demonstrated on 3 nm FinFET technology. The test chip measurement results show that it achieves a 5.9% increase in Fmax at high voltage ranges. In addition, the memory density is 21.1 Mb/mm2, and Fmax is 4.3 GHz, resulting in a figure of merit (FoM) of 90.7 GHz × Mb/mm2/V.