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Arithmetic vs. Algorithmic Fault Tolerance for Highly Scaled VLSI Signal Processors


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Adaptive fault tolerance (AFT) takes advantage of adaptive signal processing architectures that use adaptive principles to achieve automatic fault recovery. Recent work has demonstrated the capability of AFT methods to mask single and multiple stuck-at bit errors in the filter coefficients, as well as to demonstrate the capability of AFT filters to recover from transient errors. This seminar explores how the principles of adaptive fault tolerance can be used effectively in adaptive VLSI processors that are prone to both hard and soft errors in highly integrated systems that are being scaled to smaller feature dimensions and reduced voltage thresholds. This seminar also includes a discussion of arithmetic fault tolerance based on arithmetic coding, involving either hardware redundancy or multiple execution redundancy (MER) strategies designed to identify and overcome transient errors. Arithmetic techniques provide powerful low-redundancy fault tolerance properties that must be introduced at VLSI design levels, whereas MER strategies generally require higher degrees of redundancy that can be introduced at software programming levels.