HLS Trojan Detection using Machine Learning Technique

Hardware Trojans in high level synthesis (HLS) generated intellectual property (IP) designs pose significant security threats. The HLS frameworks, while enabling efficient hardware design from high-level descriptions to its respective register transfer level (RTL) counterpart, may introduce security vulnerabilities. These vulnerabilities allow malicious Trojan to be stealthily injected during phases like scheduling, allocation, and mux-interconnect design stage. Compromised HLS frameworks exacerbate this risk, potentially embedding backdoors or degrading IP operation in multiple ways. This presentation will discuss advanced HLS Trojan detection techniques based decision tree classifier-based machine learning model. The presentation will also focus on key hardware IP RTL features that need to be extracted and analyzed, for achieving high detection accuracy with zero false positives for specific trojans considered here, ensuring robust IP security.