Intelligent Memory and Storage Architectures for AI-Driven EDA and Silicon Lifecycle Management

AI-driven chip design, verification, and manufacturing create sustained pressures on data movement, memory efficiency, and storage throughput—requiring fresh thinking beyond traditional architectures. This lecture examines next-generation data systems for EDA pipelines, including tiered storage, NVMe/flash acceleration, data locality optimization, parallel I/O, and real-time structure-aware retrieval. We discuss why compute acceleration alone cannot meet performance and cost targets, and how memory-centric architectures transform silicon lifecycle analytics from simulation to yield ramp. The talk delivers a forward-looking view of circuits-and-systems opportunities in a world where data shapes algorithmic capability, system design choices, and AI model scalability.