New Ingredients in the Pot - Rethink Analog IC Design
SAR is widely used for medium resolution applications due to its simplicity, scaling compatibility, and low-power consumption. However, its power efficiency degrades as the resolution increases due to its tight requirement on the comparator noise and the exponentially growing capacitor DAC array. By contrast, DS ADC is a popular architecture for high-resolution applications. Taking advantage of noise shaping, it can achieve high resolution with a lowresolution quantizer and DAC. However, it typically requires the use of op-amps that are power hungry and scaling unfriendly. This talk will present latest hybrid ADCs that aim to combine the merits of SAR and DS while simultaneously obviating their drawbacks. After providing a high- 2019-2021 CASS Distinguished Lecturer Roster level review of published works, this talk will take a deep dive into two interesting noise-shaping SAR ADC architectures. The first one uses fully passive switched-capacitor filter to achieve 2ndorder noise shaping. It is fully dynamic and can be easily duty cycled. In addition, it is robust and calibration free. Thus, it is well suited for low-power sensor applications. The second one adopts an error-feedback structure, which simplifies the filter design. It consumes very low power by using a dynamic amplifier and address its process, voltage, and temperature (PVT) sensitivity via a fast-convergence background calibration loop.