Materials-Device-Circuits-Systems Co-optimization for Advanced Logic 2nm Node and Beyond

Systems Technology Co-optimization (STCO) and Design Technology Co-optimization (DTCO) have driven numerous logic technology innovations over many generations. As each new node introduces increased complexity and a growing number of technological advancements, it is essential to expand the traditional STCO and DTCO flows to include materials modeling. This paper demonstrates the application of a Materials-Device-Circuit-Systems Co-optimization platform by exploring various front-end-of-line (FEOL), middle-of-line (MOL), and back-end-of-line (BEOL) technologies for the 2nm logic node and beyond. We focus on Gate-All-Around (GAA) and Complementary FET (CFET) transistors, combined with Front Side (FS) and Back Side (BS) Power Delivery Networks (PDNs). We will illustrate the impact of materials on multiple circuits, including Ring Oscillators, SRAM, and larger systems such as CPU and AI accelerators.