Title
Systematic Design of a 3.5 GS/s 11-bit Time-Interleaved SAR ADC in 28 nm CMOS Achieving 54 dB SNDR at Nyquist Frequency
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June 2025 TCAS-I Highlight
Paper Title: “Systematic Design of a 3.5 GS/s 11-bit Time-Interleaved SAR ADC in 28 nm CMOS Achieving 54 dB SNDR at Nyquist Frequency”
Authored by: Shuai Liu, Yechen Tian, Congyang Sun, Guoyu Li, Hao Xu, Na Yan
Volume: 72, Issue: 6, June 2025