Thermal-Centric Design Methodologies for Monolithic 3D Integrated Circuits
Vertical integration has emerged as a game-changer technology to achieve higher device density, functional heterogeneity, and shorter wirelengths for intra-chip communication. Among various 3D technologies, monolithic 3D (M3D) ICs achieve unprecedented device and interconnect density due to sequential fabrication of multiple device tiers and vertical interconnects with diameters in the range of tens of nanometers. A fundamental challenge in dense integration technologies is the effective consideration of thermal constraints during the design process. In the first part of this talk, I will first provide a brief overview of 3D technologies, highlighting the recent advances and challenges related to the fabrication processes. I will then discuss the unique thermal characteristics of M3D ICs, describing the major differences with through silicon via (TSV) based 3D ICs. These results will rely on thermal simulations of M3D systems by leveraging a process design kit and cell library that we developed. I will also present a thermal-centric design optimization methodology for M3D integrated deep neural network (DNN) accelerators and demonstrate how technology-dataflow co-design can achieve an order of magnitude improvement in inference per second per Watt per footprint. In the second part of the talk, I will focus on the thermal crosstalk among the tiers and how such crosstalk can be used by an adversary to establish high bandwidth thermal covert-channels. I will finish the talk by proposing a new technique to dynamically detect such thermal covert-channels in M3D ICs.