CASS-Wide Webinar Talk II: "Recent Progresses of RRAM Compute-in-Memory Prototype Chips"
In this presentation, we will present the recent progresses on the compute-in-memory (CIM) prototype chips using the resistive random access memory (RRAM) technology. Mixed-signal RRAM based CIM can process the multiply-accumulate (MAC) functions in deep neural networks efficiently using the integrated analog-to-digital converter (ADC), thus it is regarded as a competitive solution for AI hardware design for edge intelligence. In collaboration with TSMC Corporate Research, we taped out two generations of RRAM CIM macros in TSMC 40 nm process.
The following features are supported in these prototype chips:
- Adaptive input sparsity control
- Reconfigurable weight precision
- Integrated digital compute units
- Input-aware on-chip ADC reference
- On-chip write-verify controller
- Input encoding for embedded security
- ADC-less communication between sub-arrays with pulse-width-modulation
- In-situ error correction code that preserves the MAC parallelism
Finally, the prospects and challenges of CIM chip design will be summarized.
This talk will take place on 16 November 2022 at 9:00 AM EST (-5:00 UTC) and features a talk by Shimeng Yu titled "Recent Progresses of RRAM Compute-in-Memory Prototype Chips".
Registration for this series is entirely free and will be limited to the first 1000 registrants per event. If you cannot register, you can also attend the webinar via Facebook Live or access the webinar recording on the IEEE CASS Resource Center.
Shimeng Yu is currently an associate professor of electrical and computer engineering at the Georgia Institute of Technology. He received a B.S. degree in microelectronics from Peking University in 2009, and an M.S. degree and Ph.D. degree in electrical engineering from Stanford University in 2011 and 2013, respectively. From 2013 to 2018, he was an assistant professor at Arizona State University.
Prof. Yu’s research interests are the semiconductor devices and integrated circuits for energy-efficient computing systems. His research expertise is on the emerging non-volatile memories for applications such as deep learning accelerator, in-memory computing, 3D integration, and hardware security. Among Prof. Yu’s honors, he was a recipient of the NSF Faculty Early CAREER Award in 2016, the IEEE Electron Devices Society (EDS) Early Career Award in 2017, the ACM Special Interests Group on Design Automation (SIGDA) Outstanding New Faculty Award in 2018, Semiconductor Research Corporation (SRC) Young Faculty Award in 2019, IEEE Circuits and Systems Society (CASS) Distinguished Lecturer, and IEEE Electron Devices Society (EDS) Distinguished Lecturer, etc.
Prof. Yu has served many premier conferences as technical program committee, including IEEE International Electron Devices Meeting (IEDM), IEEE Symposium on VLSI Technology and Circuits, IEEE International Reliability Physics Symposium (IRPS), ACM/IEEE Design Automation Conference (DAC), ACM/IEEE Design, Automation & Test in Europe (DATE), ACM/IEEE International Conference on Computer-Aided-Design (ICCAD), etc. He is serving an editor for IEEE Electron Device Letters (EDL). He is a senior member of the IEEE.